Patents by Inventor Kevin Kornegay

Kevin Kornegay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11240752
    Abstract: Methods and systems are provided for managing a smart antenna system to maximize energy efficiency while maintaining spectral efficiency and signal integrity. In accordance with certain aspects of a particularly preferred embodiment, antenna beamforming may be optimized at a base station by combining a recursive least squares beamforming technique with Kaiser windowing functions to enable side lobe cancellation in the emitted beam, thus enhancing the capacity and service quality of smart antenna systems. With respect to further aspects of a particularly preferred embodiment, processing methods may be implemented at the base station of a cellular network to cluster mobile stations in a way that improves overall energy efficiency of a base station in the cellular network.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: February 1, 2022
    Assignee: Morgan State University
    Inventors: Hailu Kassa, Kevin Kornegay
  • Publication number: 20200252869
    Abstract: Methods and systems are provided for managing a smart antenna system to maximize energy efficiency while maintaining spectral efficiency and signal integrity. In accordance with certain aspects of a particularly preferred embodiment, antenna beamforming may be optimized at a base station by combining a recursive least squares beamforming technique with Kaiser windowing functions to enable side lobe cancellation in the emitted beam, thus enhancing the capacity and service quality of smart antenna systems. With respect to further aspects of a particularly preferred embodiment, processing methods may be implemented at the base station of a cellular network to cluster mobile stations in a way that improves overall energy efficiency of a base station in the cellular network.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 6, 2020
    Inventors: Hailu Kassa, Kevin Kornegay
  • Patent number: 7615788
    Abstract: A device and method of forming electronics and microelectromechanical on a silicon carbide substrate having a slow etch rate is performed by forming circuitry on the substrate. A protective layer is formed over the circuitry having a slower etch rate than the etch rate of the silicon carbide substrate. Microelectromechanical structures supported by the substrate are then formed. The circuitry comprises a field effect transistor in one embodiment, and the protective layer comprises a heavy metal layer.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: November 10, 2009
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Kevin Kornegay, Andrew R. Atwell, Mihaela Balseanu, Jon Duster, Eskinder Hailu, Ce Li
  • Publication number: 20080093605
    Abstract: A device and method of forming electronics and microelectromechanical on a silicon carbide substrate having a slow etch rate is performed by forming circuitry on the substrate. A protective layer is formed over the circuitry having a slower etch rate than the etch rate of the silicon carbide substrate. Microelectromechanical structures supported by the substrate are then formed. The circuitry comprises a field effect transistor in one embodiment, and the protective layer comprises a heavy metal layer.
    Type: Application
    Filed: January 29, 2007
    Publication date: April 24, 2008
    Inventors: Kevin Kornegay, Andrew Atwell, Mihaela Balseanu, Jon Duster, Eskinder Hailu, Ce Li
  • Patent number: 7215194
    Abstract: Circuit topologies that provide extended bandwidth of operation are disclosed. The circuits have two stages that share inductors, in which in-phase current components sum at a summing node and flow together, increasing the magnitude of the current in the inductors. The inductive peaking exhibited by the circuits is increased without using excessively large inductors.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: May 8, 2007
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Daniel Kucharski, Kevin Kornegay
  • Patent number: 7170141
    Abstract: A method of forming electronics and microelectromechanical on a silicon carbide substrate having a slow etch rate is performed by forming circuitry on the substrate. A protective layer is formed over the circuitry having a slower etch rate than the etch rate of the silicon carbide substrate. Microelectromechanical structures supported by the substrate are then formed. The circuitry comprises a field effect transistor in one embodiment, and the protective layer comprises a heavy metal layer.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: January 30, 2007
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Kevin Kornegay, Andrew R. Atwell, Mihaela Balseanu, Jon Duster, Eskinder Hailu, Ce Li
  • Patent number: 7098697
    Abstract: A circuit topology for high speed low voltage logic circuits is disclosed that reduces the number of levels of stacked active circuit elements from 3 to 2. Circuits providing a variety of logic functions are presented, including a latch, an exclusive OR gate, a combination XOR and latch, a multiplexer and a demultiplexer. Circuits built according to the principles of the invention have been operated at speeds of 40 GHz. The circuit topology can operate at supply voltages as low as 2V (for silicon or silicon-germanium based devices) and provide power saving of 25%–50% or more, depending on the logic function. In some embodiments, circuits comprising single ended or differential inputs can be provided.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: August 29, 2006
    Assignee: Cornell Research Foundation Inc.
    Inventors: Daniel Kucharski, Kevin Kornegay
  • Publication number: 20050264319
    Abstract: A circuit topology for high speed low voltage logic circuits is disclosed that reduces the number of levels of stacked active circuit elements from 3 to 2. Circuits providing a variety of logic functions are presented, including a latch, an exclusive OR gate, a combination XOR and latch, a multiplexer and a demultiplexer. Circuits built according to the principles of the invention have been operated at speeds of 40 GHz. The circuit topology can operate at supply voltages as low as 2V (for silicon or silicon-germanium based devices) and provide power saving of 25%-50% or more, depending on the logic function. In some embodiments, circuits comprising single ended or differential inputs can be provided.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 1, 2005
    Applicant: Cornell Research Foundation, Inc.
    Inventors: Daniel Kucharski, Kevin Kornegay
  • Publication number: 20050264356
    Abstract: Circuit topologies that provide extended bandwidth of operation are disclosed. The circuits have two stages that share inductors, in which in-phase current components sum at a summing node and flow together, increasing the magnitude of the current in the inductors. The inductive peaking exhibited by the circuits is increased without using excessively large inductors.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 1, 2005
    Applicant: Cornell Research Foundation, Inc.
    Inventors: Daniel Kucharski, Kevin Kornegay
  • Publication number: 20050218994
    Abstract: Circuits for converting an input current to an output voltage that employs a uniquely biased common-gate or common-base stage as a current buffer and a direct drive of the current buffer output into an impedance to convert the current signal to a voltage signal.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Applicant: Cornell Research Foundation, Inc.
    Inventors: Drew Guckenberger, Kevin Kornegay
  • Publication number: 20040077164
    Abstract: A method of forming electronics and microelectromechanical on a silicon carbide substrate having a slow etch rate is performed by forming circuitry on the substrate. A protective layer is formed over the circuitry having a slower etch rate than the etch rate of the silicon carbide substrate. Microelectromechanical structures supported by the substrate are then formed. The circuitry comprises a field effect transistor in one embodiment, and the protective layer comprises a heavy metal layer.
    Type: Application
    Filed: March 7, 2003
    Publication date: April 22, 2004
    Inventors: Kevin Kornegay, Andrew R. Atwell, Mihaela Balseanu, Jon Duster, Eskinder Hailu, Ce Li