Patents by Inventor Kevin L. Beaman

Kevin L. Beaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8518184
    Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kevin L. Beaman, Trung T. Doan, Lyle D. Breiner, Ronald A. Weimer, Er-Xuan Ping, David J. Kubista, Cem Basceri, Lingyi A. Zheng
  • Patent number: 8384192
    Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 ?.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: February 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Lingyi A. Zheng, Trung T. Doan, Lyle D. Breiner, Er-Xuan Ping, Kevin L. Beaman, Ronald A. Weimer, Cem Basceri, David J. Kubista
  • Patent number: 8030170
    Abstract: Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500° C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700° C. to about 1000° C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: October 4, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Yunjun Ho, Matt Meyers, Kevin L. Beaman, Gregory J. Light
  • Patent number: 8017470
    Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 ? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: September 13, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Kevin L. Beaman, John T. Moore
  • Publication number: 20110163416
    Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 ?.
    Type: Application
    Filed: March 14, 2011
    Publication date: July 7, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Lingyi A. Zheng, Trung T. Doan, Lyle D. Breiner, Er-Xuan Ping, Kevin L. Beaman, Ronald A. Weimer, Cem Basceri, David J. Kubista
  • Publication number: 20110136319
    Abstract: Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500° C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700° C. to about 1000° C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 9, 2011
    Inventors: Yunjun Ho, Matt Meyers, Kevin L. Beaman, Gregory J. Light
  • Patent number: 7919829
    Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: April 5, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Jigish D. Trivedi, Robert D. Patraw, Kevin L. Beaman, John A. Smythe, III
  • Patent number: 7906393
    Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 ?.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: March 15, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Lingyi A. Zheng, Trung T. Doan, Lyle D. Breiner, Er-Xuan Ping, Kevin L. Beaman, Ronald A. Weimer, Cem Basceri, David J. Kubista
  • Publication number: 20100282164
    Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
    Type: Application
    Filed: July 20, 2010
    Publication date: November 11, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kevin L. Beaman, Trung T. Doan, Lyle D. Breiner, Ronald A. Weimer, Er-Xuan Ping, David J. Kubista, Cem Basceri, Lingyi A. Zheng
  • Publication number: 20100267226
    Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 ? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
    Type: Application
    Filed: June 23, 2010
    Publication date: October 21, 2010
    Applicant: Round Rock Research, LLC
    Inventors: Kevin L. Beaman, John T. Moore
  • Patent number: 7803678
    Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: September 28, 2010
    Assignee: Round Rock Research, LLC
    Inventors: Kevin L. Beaman, John T. Moore
  • Patent number: 7771537
    Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: August 10, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin L. Beaman, Trung T. Doan, Lyle D. Breiner, Ronald A. Weimer, Er-Xuan Ping, David J. Kubista, Cem Basceri, Lingyi A. Zheng
  • Patent number: 7651910
    Abstract: The invention includes a method of forming a programmable memory device. A tunnel oxide is formed to be supported by a semiconductor substrate. A stack is formed over the tunnel oxide. The stack comprises a floating gate, dielectric mass and control gate. The stack has a top, and has opposing sidewalls extending downwardly from the top. The dielectric mass includes silicon nitride. Silicon nitride spacers are formed along sidewalls of the stack, and a silicon nitride cap is formed over a top of the stack. The silicon nitride within the dielectric mass, cap and/or sidewall spacers is formed from trichlorosilane and ammonia.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: January 26, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin L. Beaman, Ronald A. Weimer
  • Patent number: 7647886
    Abstract: Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one embodiment, the system includes a gas phase reaction chamber, a first exhaust line coupled to the reaction chamber, first and second traps each in fluid communication with the first exhaust line, and a vacuum pump coupled to the first exhaust line to remove gases from the reaction chamber. The first and second traps are operable independently to individually and/or jointly collect byproducts from the reaction chamber. It is emphasized that this Abstract is provided to comply with the rules requiring an abstract. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: January 19, 2010
    Assignee: Micron Technology, Inc.
    Inventors: David J. Kubista, Trung T. Doan, Lyle D. Breiner, Ronald A. Weimer, Kevin L. Beaman, Er-Xuan Ping, Lingyi A. Zheng, Cem Basceri
  • Patent number: 7514366
    Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: April 7, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Jigish D. Trivedi, Robert D. Patraw, Kevin L. Beaman, John A. Smythe, III
  • Publication number: 20080261388
    Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 ? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
    Type: Application
    Filed: June 25, 2008
    Publication date: October 23, 2008
    Inventors: Kevin L. Beaman, John T. Moore
  • Patent number: 7422635
    Abstract: The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: September 9, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Lingyi A. Zheng, Trung T. Doan, Lyle D. Breiner, Er-Xuan Ping, Kevin L. Beaman, Ronald A. Weimer, David J. Kubista, Cem Basceri
  • Patent number: 7399714
    Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 ? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: July 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kevin L. Beaman, John T. Moore
  • Patent number: 7371647
    Abstract: The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 ? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer. The invention encompasses a method of forming a pair of transistors associated with a semiconductor substrate. First and second regions of the substrate are defined. A first oxide region is formed to cover the first region of the substrate, and to not cover the second region of the substrate. Nitrogen is formed within the first oxide region, and a first conductive layer is formed over the first oxide region. After the first conductive layer is formed, a second oxide region is formed over the second region of the substrate.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: May 13, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kevin L. Beaman, John T. Moore
  • Patent number: 7344755
    Abstract: The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have particular utility in depositing TiN in a batch process. One implementation involves pretreating a surface of a process chamber by contemporaneously introducing first and second pretreatment precursors (e.g., TiCl4 and NH3) to deposit a pretreatment material on a the chamber surface. After the pretreatment, the first microfeature workpiece may be placed in the chamber and TiN may be deposited on the microfeature workpiece by alternately introducing quantities of first and second deposition precursors.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: March 18, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kevin L. Beaman, Ronald A. Weimer, Lyle D. Breiner, Er-Xuan Ping, Trung T. Doan, Cem Basceri, David J. Kubista, Lingyi A. Zheng