Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

Abstract: A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.

Abstract: Disclosed herein are IC structures, packages, and devices that include recesses processed via selective growth. An example integrated circuit (IC) structure, includes a first dielectric material, a second dielectric material on the first dielectric material, and a recess in the second dielectric material, wherein the recess includes a bottom, a top, and sidewalls. The IC further includes a first material within the recess and at a bottom of the recess, wherein the first material includes a metal and oxygen, a self-assembled monolayer (SAM) material, or an organic material, and a second material within the recess and between the first material and the top of the recess, wherein the second material is in contact with the sidewalls of the recess.

Abstract: A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.

Abstract: An integrated circuit includes a base comprising an insulating dielectric. A plurality of conductive lines extends vertically above the base in a spaced-apart arrangement, the plurality including a first conductive line and a second conductive line adjacent to the first conductive line. A void is between the first and second conductive lines. A cap of insulating material is located above the void and defines an upper boundary of the void such that the void is further located between the base and the cap of insulating material. In some embodiments, one or more vias contacts an upper end of one or more of the conductive lines.

Abstract: Disclosed herein are peripheral inductors for integrated circuits (ICs), as well as related methods and devices. In some embodiments, an IC device may include a die having an inductor extending around at least a portion of a periphery of the die.

Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.

Abstract: Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive traces may include a first conductive trace surrounded by a second and third conductive traces. The substrate also includes a photoresist block in a region of the ILD. The region may be directly surrounded by the ILD and first conductive trace, and the photoresist block may be between the first conductive trace. The photoresist block may have a top surface that is substantially coplanar to top surfaces of the ILD and conductive traces. The photoresist block may have a width substantially equal to a width of the conductive traces. The photoresist block may be in the first conductive trace and between the second and third conductive traces. The photoresist block may include a metal oxide core embedded with organic ligands.

Abstract: Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, an integrated circuit structure includes a substrate. A plurality of alternating first and second conductive lines is along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate. A conductive via is on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via centered over the one of the conductive lines. A second ILD layer is above plurality of alternating first and second conductive lines and laterally adjacent to the conductive via. The second ILD layer has an uppermost surface substantially co-planar with the flat top surface of the conductive via.

Abstract: Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.

Abstract: Disclosed herein are inductor/core assemblies for integrated circuits (ICs), as well as related structures, methods, and devices. In some embodiments, an IC structure may include an inductor and a magnetic core in an interior of the inductor. The magnetic core may be movable perpendicular to a plane of the inductor.

Abstract: Disclosed herein are integrated circuit (IC) components with substrate cavities, as well as related techniques and assemblies. In some embodiments, an IC component may include a substrate, a device layer on the substrate, a plurality of interconnect layers on the device layer, and a cavity in the substrate.

Abstract: An embodiment includes a dielectric material; a trench included in the dielectric material, the trench having first and second opposing sidewalls; wherein the trench includes: (a)(i) a first trench portion extending from the first sidewall to the second sidewall, (a)(ii) a second trench portion extending from the first sidewall to the second sidewall, and (a)(iii) a third trench portion extending from the first sidewall to the second sidewall; wherein the second trench portion is between the first trench portion and the third trench portion; wherein the first trench portion is substantially filled with a first material, the second trench portion is substantially filled with a second material, and the third trench portion is substantially filled with a third material; wherein (b)(i) the first material includes nitrogen, and (b)(ii) the first material includes more nitrogen than the third material. Other embodiments are described herein.

Abstract: There is disclosed in an example an integrated circuit, including: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; a dielectric plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect; and a dielectric cap covering the dielectric plug.

Abstract: Techniques are disclosed that enable independent control of interconnect lines and line end structures using a single mask. The techniques provided are particularly useful, for instance, where single mask lithography processes limit the scaling of line end structures. In some embodiments, the techniques can be implemented using a liner body and multiple angled etches of the liner body to provide a line end structure comprised of a remaining portion of the liner body. In such cases, the line end structure material enables an etch rate that is slower than the etch rate of surrounding insulator materials. Furthermore, the line end structure can be of minimal size not attainable using conventional single mask processes. In other embodiments, the techniques can be implemented using a hardmask that includes hardmask features defining lines, and one or more angled etches of the hardmask to provide line end structure(s) of minimal size.

Abstract: In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.