Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

Abstract: An embodiment includes a dielectric material; a trench included in the dielectric material, the trench having first and second opposing sidewalls; wherein the trench includes: (a)(i) a first trench portion extending from the first sidewall to the second sidewall, (a)(ii) a second trench portion extending from the first sidewall to the second sidewall, and (a)(iii) a third trench portion extending from the first sidewall to the second sidewall; wherein the second trench portion is between the first trench portion and the third trench portion; wherein the first trench portion is substantially filled with a first material, the second trench portion is substantially filled with a second material, and the third trench portion is substantially filled with a third material; wherein (b)(i) the first material includes nitrogen, and (b)(ii) the first material includes more nitrogen than the third material. Other embodiments are described herein.

Abstract: A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity.

Abstract: In an example, there is disclosed a configurable impedance element, having: a first impedance network including a plurality of series impedance elements and providing an initial impedance; a trim impedance network parallel to the first impedance network, including a plurality of corresponding impedance elements to the impedance elements of the first impedance network; and antifuses between the impedance elements of the first impedance network and their corresponding impedance elements of the trim network. There is also disclosed an integrated circuit including the impedance element, and a method of manufacturing and configuring the impedance element.

Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

Abstract: There is disclosed in an example an integrated circuit, including: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; a dielectric plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect; and a dielectric cap covering the dielectric plug.

Abstract: Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, an integrated circuit structure includes a substrate. A plurality of alternating first and second conductive lines is along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate. A conductive via is on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via centered over the one of the conductive lines. A second ILD layer is above plurality of alternating first and second conductive lines and laterally adjacent to the conductive via. The second ILD layer has an uppermost surface substantially co-planar with the flat top surface of the conductive via.

Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

Abstract: Rendering techniques are disclosed for displays capable of adjusting/changing the angle of individual pixels (or pixel groups), referred to herein as textured displays. The textured displays may be capable of creating on demand textures which may be used to simulate the surface of an object in a scene. The rendering techniques may be used to improve upon the realism of rendered scenes/objects and they may provide users with a unique rendering experience whereby the textured display physically changes to mimic textures of the rendered scenes/objects. This can be achieved by sending geometric data, such as surface normal information, to individual pixels of the textured display. Other factors may be considered when adjusting the angle of individual pixels of the textured display, such as whether the user is experiencing too much glare.

Abstract: Techniques are disclosed for improving energy efficiency of displays, and in particular, displays capable of selective refresh. In an embodiment, the techniques include adjusting the effective resolution of a display based on the viewer's distance from the display. The effective resolution adjustment can be accomplished by, for example, grouping individual pixels or blurring the display buffer (or both pixel grouping and blurring) based on the viewer's distance from the display. Such an adjustment has the effect of creating enlarged pixels from a plurality of smaller pixels. In any such cases, each of the enlarged pixels (also called macro-pixels) can then be selectively refreshed based on changes from the previous frame. In addition, even if one of the macro-pixels has changed from the last frame, it also need not be refreshed if the viewer would not perceive that change given a subtle or otherwise unperceivable difference in intensity.

Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.

Abstract: A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity. Also described are various approaches to fabricating a semiconductor package having a hermetically sealed region.

Abstract: Techniques and mechanisms to provide for metering acceleration. In an embodiment, a microelectromechanical accelerometer includes a magnet, a mass, and a first support beam portion and second support beam portion for suspension of the mass. Resonance frequency characteristics of the first support beam portion and second support beam portion, based on the magnet and a current conducted by the first support beam portion and second support beam portion, are indicative of acceleration of the mass. In another embodiment, the accelerometer further includes a first wire portion and a second wire portion which are each coupled to the mass and further coupled to a respective anchor for exchanging a signal with the first wire portion and the second wire portion. The first wire portion and the second wire portion provide for biasing of the mass.

Abstract: A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity. Also described are various approaches to fabricating a semiconductor package having a hermetically sealed region.

Abstract: Techniques are disclosed for improving energy efficiency of displays, and in particular, displays capable of selective refresh. In an embodiment, the techniques include adjusting the effective resolution of a display based on the viewer's distance from the display. The effective resolution adjustment can be accomplished by, for example, grouping individual pixels or blurring the display buffer (or both pixel grouping and blurring) based on the viewer's distance from the display. Such an adjustment has the effect of creating enlarged pixels from a plurality of smaller pixels. In any such cases, each of the enlarged pixels (also called macro-pixels) can then be selectively refreshed based on changes from the previous frame. In addition, even if one of the macro-pixels has changed from the last frame, it also need not be refreshed if the viewer would not perceive that change given a subtle or otherwise unperceivable difference in intensity.

Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.