Patents by Inventor Kevin L. Lin

Kevin L. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150091890
    Abstract: Rendering techniques are disclosed for displays capable of adjusting/changing the angle of individual pixels (or pixel groups), referred to herein as textured displays. The textured displays may be capable of creating on demand textures which may be used to simulate the surface of an object in a scene. The rendering techniques may be used to improve upon the realism of rendered scenes/objects and they may provide users with a unique rendering experience whereby the textured display physically changes to mimic textures of the rendered scenes/objects. This can be achieved by sending geometric data, such as surface normal information, to individual pixels of the textured display. Other factors may be considered when adjusting the angle of individual pixels of the textured display, such as whether the user is experiencing too much glare.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Nathan R. Andrysco, Kevin L. Lin
  • Patent number: 8975138
    Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 10, 2015
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Hui Jae Yoo, Yan A. Borodovsky, Florian Gstrein, David N. Shykind, Kevin L. Lin
  • Publication number: 20150001724
    Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Manish CHANDHOK, Hui Jae Yoo, Yan A. Borodovsky, Florian Gstrein, David N. Shykind, Kevin L. Lin
  • Publication number: 20140182377
    Abstract: Techniques and mechanisms to provide for metering acceleration. In an embodiment, a microelectromechanical accelerometer includes a magnet, a mass, and a first support beam portion and second support beam portion for suspension of the mass. Resonance frequency characteristics of the first support beam portion and second support beam portion, based on the magnet and a current conducted by the first support beam portion and second support beam portion, are indicative of acceleration of the mass. In another embodiment, the accelerometer further includes a first wire portion and a second wire portion which are each coupled to the mass and further coupled to a respective anchor for exchanging a signal with the first wire portion and the second wire portion. The first wire portion and the second wire portion provide for biasing of the mass.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Kevin L. Lin, Faras Eid, Qing Ma
  • Patent number: 8633551
    Abstract: A semiconductor package having a mechanical fuse therein and methods to form a semiconductor package having a mechanical fuse therein are described. For example, a semiconductor structure includes a semiconductor package. A semiconductor die is housed in the semiconductor package. A microelectromechanical system (MEMS) device is housed in the semiconductor package. The MEMS device has a suspended portion. A mechanical fuse is housed in the semiconductor package and either coupled to, or decoupled from, the suspended portion of the MEMS device.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: January 21, 2014
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Kevin L. Lin, Feras Eid, Qing Ma
  • Publication number: 20140002178
    Abstract: A semiconductor package having a mechanical fuse therein and methods to form a semiconductor package having a mechanical fuse therein are described. For example, a semiconductor structure includes a semiconductor package. A semiconductor die is housed in the semiconductor package. A microelectromechanical system (MEMS) device is housed in the semiconductor package. The MEMS device has a suspended portion. A mechanical fuse is housed in the semiconductor package and either coupled to, or decoupled from, the suspended portion of the MEMS device.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Weng Hong Teh, Kevin L. Lin, Feras Eid, Qing Ma
  • Publication number: 20140000377
    Abstract: A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity. Also described are various approaches to fabricating a semiconductor package having a hermetically sealed region.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Kevin L. Lin, Qing Ma, Feras Eid, Johanna Swan, Weng Hong Teh