Patents by Inventor Kevin Van Horn

Kevin Van Horn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scalable processor to processor and processor to I/O interconnection network and method for parallel processing arrays
    Patent number: 5598408
    Abstract: A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.
    Type: Grant
    Filed: January 14, 1994
    Date of Patent: January 28, 1997
    Assignee: MasPar Computer Corporation
    Inventors: John R. Nickolls, John Zapisek, Won S. Kim, Jeffrey C. Kalb, W. Thomas Blank, Eliot Wegbreit, Kevin Van Horn
  • Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays
    Patent number: 5280474
    Abstract: A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.
    Type: Grant
    Filed: January 5, 1990
    Date of Patent: January 18, 1994
    Assignee: Maspar Computer Corporation
    Inventors: John R. Nickolls, John Zapisek, Won S. Kim, Jeffery C. Kalb, W. Thomas Blank, Eliot Wegbreit, Kevin Van Horn