Patents by Inventor Kewei Zuo
Kewei Zuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230223287Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.Type: ApplicationFiled: March 14, 2023Publication date: July 13, 2023Inventors: Tzu-Cheng LIN, Y.Y. PENG, Jerry WANG, Kewei ZUO, Chien Rhone WANG
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Patent number: 11626304Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.Type: GrantFiled: February 18, 2021Date of Patent: April 11, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Cheng Lin, Y. Y. Peng, Jerry Wang, Kewei Zuo, Chien Rhone Wang
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Publication number: 20220269184Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.Type: ApplicationFiled: February 25, 2021Publication date: August 25, 2022Inventors: Tzu-Cheng LIN, Chien Rhone WANG, Kewei ZUO, Ming-Tan LEE, Zi-Jheng LIU
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Publication number: 20210175105Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.Type: ApplicationFiled: February 18, 2021Publication date: June 10, 2021Inventors: Tzu-Cheng LIN, Y.Y. PENG, Jerry WANG, Kewei ZUO, Chien Rhone WANG
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Patent number: 10964566Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.Type: GrantFiled: May 7, 2019Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Go., Ltd.Inventors: Tzu-Cheng Lin, Y.Y. Peng, Jerry Wang, Kewei Zuo, Chien Rhone Wang
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Publication number: 20200006102Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.Type: ApplicationFiled: May 7, 2019Publication date: January 2, 2020Inventors: Tzu-Cheng Lin, Y.Y. Peng, Jerry Wang, Kewei Zuo, Chien Rhone Wang
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Patent number: 10054938Abstract: A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity.Type: GrantFiled: May 7, 2015Date of Patent: August 21, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung Cheng Ko, Tzu-Yu Wang, Kewei Zuo, Kuan Teng Lo, Chien Rhone Wang, Chih-Wei Lai
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Patent number: 9698030Abstract: A temperature controlled loadlock chamber for use in semiconductor processing is provided. The temperature controlled loadlock chamber may include one or more of an adjustable fluid pump, mass flow controller, one or more temperature sensors, and a controller. The adjustable fluid pump provides fluid having a predetermined temperature to a temperature-controlled plate. The mass flow controller provides gas flow into the chamber that may also aid in maintaining a desired temperature. Additionally, one or more temperature sensors may be combined with the adjustable fluid pump and/or the mass flow controller to provide feedback and to provide a greater control over the temperature. A controller may be added to control the adjustable fluid pump and the mass flow controller based upon temperature readings from the one or more temperature sensors.Type: GrantFiled: November 10, 2014Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Lin, Jyh-Cherng Sheu, Ming-Feng Yoo, Kewei Zuo
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Patent number: 9588505Abstract: Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled.Type: GrantFiled: April 25, 2013Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Wang, Chen-Hua Yu, Chien Rhone Wang, Henry Lo, Jung Cheng Ko, Chih-Wei Lai, Kewei Zuo
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Patent number: 9508653Abstract: A method includes recording a wafer ID and a location ID of a device die in a database, and bonding the device die over a package substrate, wherein the device die and the package substrate are disposed in a package. A package ID is on the package. A mapping is established to link the wafer ID and the location ID of the device die to the package ID.Type: GrantFiled: September 18, 2013Date of Patent: November 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kewei Zuo, Wen-Yao Chang, Chien Rhone Wang
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Patent number: 9390491Abstract: A system and method is disclosed for a quality control and/or inspection procedure for assembly line processes. The disclosed system and method enable automatic optical inspection of a device during different stages of manufacture as well as in its finished form. The disclosed system and method enable the automatic quality control process to be self-learning, dynamic, and to identify and classify defects in real time.Type: GrantFiled: January 30, 2013Date of Patent: July 12, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kewei Zuo, Chien Rhone Wang, Tzu-Cheng Lin, Chih-Wei Lai
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Patent number: 9390060Abstract: Packaging methods, material dispensing methods and apparatuses, and automatic measurement systems are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a second die to a top surface of a first die, dispensing a first amount of underfill material between the first die and the second die, and capturing an image of the underfill material. Based on the image captured, a second amount or no additional amount of underfill material is dispensed between the first die and the second die.Type: GrantFiled: March 14, 2012Date of Patent: July 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Rhone Wang, Chih-Wei Lai, Chih-Chiang Chang, Kewei Zuo, Jing-Cheng Lin
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Patent number: 9177843Abstract: A semiconductor manufacturing line includes an inert environment selected from the group consisting essentially of an inert airtight wafer holder, an inert wafer transport channel, an inert production tool, an inert clean room, and combinations thereof.Type: GrantFiled: June 29, 2007Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Ming Sung, Simon Wang, Jia-Ren Chen, Henry Lo, Chen-Hua Yu, Jean Wang, Kewei Zuo
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Patent number: 9153506Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.Type: GrantFiled: July 6, 2012Date of Patent: October 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Rhone Wang, Kewei Zuo, Chen-Hua Yu, Jing-Cheng Lin, Yen-Hsin Liu
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Publication number: 20150241876Abstract: A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity.Type: ApplicationFiled: May 7, 2015Publication date: August 27, 2015Inventors: Jung Cheng Ko, Tzu-Yu Wang, Kewei Zuo, Kuan Teng Lo, Chien Rhone Wang, Chih-Wei Lai
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Patent number: 9037279Abstract: A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity.Type: GrantFiled: July 7, 2010Date of Patent: May 19, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Francis Ko, Tzu-yu Wang, Kewei Zuo, Henry Lo, Jean Wang, Chih-Wei Lai
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Publication number: 20150132100Abstract: A temperature controlled loadlock chamber for use in semiconductor processing is provided. The temperature controlled loadlock chamber may include one or more of an adjustable fluid pump, mass flow controller, one or more temperature sensors, and a controller. The adjustable fluid pump provides fluid having a predetermined temperature to a temperature-controlled plate. The mass flow controller provides gas flow into the chamber that may also aid in maintaining a desired temperature. Additionally, one or more temperature sensors may be combined with the adjustable fluid pump and/or the mass flow controller to provide feedback and to provide a greater control over the temperature. A controller may be added to control the adjustable fluid pump and the mass flow controller based upon temperature readings from the one or more temperature sensors.Type: ApplicationFiled: November 10, 2014Publication date: May 14, 2015Inventors: Chun-Hsien Lin, Jyh-Cherng Sheu, Ming-Feng Yoo, Kewei Zuo
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Patent number: 9010617Abstract: In a reflow process, a plurality of solder bumps between a first workpiece and a second workpiece is melted. During a solidification stage of the plurality of solder bumps, the plurality of solder bumps is cooled at a first cooling rate. After the solidification stage is finished, the plurality of solder bumps is cooled at a second cooling rate lower than the first cooling rate.Type: GrantFiled: January 10, 2011Date of Patent: April 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Wen-Yao Chang, Chien Rhone Wang, Kewei Zuo, Chung-Shi Liu
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Publication number: 20150079734Abstract: A method includes recording a wafer ID and a location ID of a device die in a database, and bonding the device die over a package substrate, wherein the device die and the package substrate are disposed in a package. A package ID is on the package. A mapping is established to link the wafer ID and the location ID of the device die to the package ID.Type: ApplicationFiled: September 18, 2013Publication date: March 19, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kewei Zuo, Wen-Yao Chang, Chien Rhone Wang
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Publication number: 20150051860Abstract: A method of inspecting a structure of a device and a system for doing the same is described. The method includes generating a sample image of a device having a structure to be inspected; identifying a plurality of features of the sample image; comparing the plurality of features to a corresponding plurality of features of a reference image; and locating features in the sample image that deviate from corresponding features of the reference image. The generating step includes moving the device, a detector array or both, relative to one another, wherein the detector array is configured to generate a line of data representing light reflected from the device, and assembling lines of data from the detector array to generate a sample image.Type: ApplicationFiled: August 19, 2013Publication date: February 19, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kewei ZUO, Wen-Yao CHANG, Ming-Shin SU, Chien Rhone WANG, Hsin-Hui LEE, Chih-Hao LIN