Patents by Inventor Keyan Bennaceur

Keyan Bennaceur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9991370
    Abstract: High electron mobility leads to better device performance and today is achieved by fabricating “gated devices” within a high-mobility two-dimensional electron gas (2DEG. However, the fabrication techniques used to form these devices lead to rapid degradation of the 2DEG quality which then can limits the mobility of the electronic devices. Accordingly, it would be beneficial to provide a process/technique which circumvents this processing and 2DEG layer damage. By exploiting a flip-chip methodology such damaging processing steps are separated to a second die/wafer which is then coupled to the 2DEG wafer. Extensions of the technique with two or more different semiconductor materials or material systems may be employed in conjunction with one or more electronic circuits to provide 2DEG enabled circuits in 2D and/or 3D stacked configurations. Further semiconductor materials providing EG elements may incorporate one or more of 2DEG, 1DEG, and “zero” DEG structures.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: June 5, 2018
    Assignee: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY
    Inventors: Guillaume Gervais, Keyan Bennaceur
  • Publication number: 20160172479
    Abstract: High electron mobility leads to better device performance and today is achieved by fabricating “gated devices” within a high-mobility two-dimensional electron gas (2DEG. However, the fabrication techniques used to form these devices lead to rapid degradation of the 2DEG quality which then can limits the mobility of the electronic devices. Accordingly, it would be beneficial to provide a process/technique which circumvents this processing and 2DEG layer damage. By exploiting a flip-chip methodology such damaging processing steps are separated to a second die/wafer which is then coupled to the 2DEG wafer. Extensions of the technique with two or more different semiconductor materials or material systems may be employed in conjunction with one or more electronic circuits to provide 2DEG enabled circuits in 2D and/or 3D stacked configurations. Further semiconductor materials providing EG elements may incorporate one or more of 2DEG, 1DEG, and “zero” DEG structures.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 16, 2016
    Inventors: Guillaume Gervais, Keyan Bennaceur