Patents by Inventor Khee Wooi Lee
Khee Wooi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200151364Abstract: A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.Type: ApplicationFiled: November 11, 2019Publication date: May 14, 2020Applicant: Intel CorporationInventors: Jose S. Niell, Gautham N. Chinya, Khee Wooi Lee, William A. Stevens, JR., Josh Triplett
-
Patent number: 10534935Abstract: A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.Type: GrantFiled: July 1, 2016Date of Patent: January 14, 2020Assignee: Intel CorporationInventors: Jose S. Niell, Gautham N. Chinya, Khee Wooi Lee, William A. Stevens, Jr., Josh Triplett
-
Patent number: 9990327Abstract: In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.Type: GrantFiled: October 12, 2015Date of Patent: June 5, 2018Assignee: Intel CorporationInventors: Michael T. Klinglesmith, Chang Yong Kang, Robert DeGruijl, Ioannis T. Schoinas, Darren Abramson, Khee Wooi Lee
-
Publication number: 20180004979Abstract: A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.Type: ApplicationFiled: July 1, 2016Publication date: January 4, 2018Inventors: Jose S. Niell, Gautham N. Chinya, Khee Wooi Lee, William A. Stevens, JR., Josh Triplett
-
Patent number: 9678808Abstract: A method and apparatus is disclosed herein for performing write-only inter processor reset synchronization. In one embodiment, the processing unit comprises: a communication unit to transmit information to the second processing unit; memory to store reset synchronization information and message information; and processing logic to perform write-only reset synchronization between itself and the second processing unit based on bit indications set in the memory.Type: GrantFiled: December 18, 2014Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Michael Berger, Khee Wooi Lee, Mukesh Kataria
-
Publication number: 20160357700Abstract: In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.Type: ApplicationFiled: October 12, 2015Publication date: December 8, 2016Inventors: Michael T. Klinglesmith, Chang Yong Kang, Robert DeGruijl, Ioannis T. Schoinas, Darren Abramson, Khee Wooi Lee
-
Publication number: 20160179585Abstract: A method and apparatus is disclosed herein for performing write-only inter processor reset synchronization. In one embodiment, the processing unit comprises: a communication unit to transmit information to the second processing unit; memory to store reset synchronization information and message information; and processing logic to perform write-only reset synchronization between itself and the second processing unit based on bit indications set in the memory.Type: ApplicationFiled: December 18, 2014Publication date: June 23, 2016Inventors: Michael Berger, Khee Wooi Lee, Mukesh Kataria
-
Patent number: 8930602Abstract: In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.Type: GrantFiled: August 31, 2011Date of Patent: January 6, 2015Assignee: Intel CorporationInventors: Kie Woon Lim, E-Liang Chew, Khee Wooi Lee, Darren L. Abramson
-
Publication number: 20130054856Abstract: In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Inventors: Kie Woon Lim, E-Liang Chew, Khee Wooi Lee, Darren L. Abramson
-
Patent number: 8386682Abstract: Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.Type: GrantFiled: June 30, 2010Date of Patent: February 26, 2013Assignee: Intel CorporationInventors: Kah Meng Yeem, Mikal C. Hunsaker, Darren L. Abramson, Raul N. Gutierrez, Khee Wooi Lee
-
Patent number: 8364915Abstract: Techniques for generating access information indicating a least recently used (LRU) memory region in a set of memory regions. In an embodiment, data is stored in an entry of an LRU tracking list (LTL) based on a touch message indicating when a memory group has been touched—e.g. read from, written to and/or associated with a memory region. The data stored in an LTL entry may include an identifier of a memory group and/or validity data specifying whether that LTL entry stores a set of default data. In another embodiment, access information may be generated based on the memory group identifier and the validity data.Type: GrantFiled: June 23, 2010Date of Patent: January 29, 2013Assignee: Intel CorporationInventors: Kie Woon Lim, Khee Wooi Lee, William A. Stevens, Jr.
-
Publication number: 20120005386Abstract: Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Inventors: Kah Meng Yeem, Mikal C. Hunsaker, Darren L. Abramson, Raul N. Gutierrez, Khee Wooi Lee
-
Publication number: 20110320742Abstract: Techniques for generating access information indicating a least recently used (LRU) memory region in a set of memory regions. In an embodiment, data is stored in an entry of an LRU tracking list (LTL) based on a touch message indicating when a memory group has been touched—e.g. read from, written to and/or associated with a memory region. The data stored in an LTL entry may include an identifier of a memory group and/or validity data specifying whether that LTL entry stores a set of default data. In another embodiment, access information may be generated based on the memory group identifier and the validity data.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Inventors: Kie Woon Lim, Khee Wooi Lee, William A. Stevens, JR.
-
Patent number: 7990999Abstract: Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams.Type: GrantFiled: January 14, 2009Date of Patent: August 2, 2011Assignee: Intel CorporationInventors: Khee Wooi Lee, Mikal C. Hunsaker, Darren L. Abramson
-
Publication number: 20090119432Abstract: Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams.Type: ApplicationFiled: January 14, 2009Publication date: May 7, 2009Inventors: Khee Wooi Lee, Mikal C. Hunsaker, Darren L. Abramson
-
Patent number: 7525986Abstract: Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams.Type: GrantFiled: October 28, 2004Date of Patent: April 28, 2009Assignee: Intel CorporationInventors: Khee Wooi Lee, Mikal C. Hunsaker, Darren L. Abramson
-
Publication number: 20080288689Abstract: In one embodiment, an arbiter may provide for opportunistic granting of one or more grants to a requestor that has no available fixed grants remaining in a given arbitration round. In one embodiment, a method may detect that a target resource to be accessed by a requestor with a valid grant count is unavailable during an arbitration round, and opportunistically grant an access grant to another requestor to access a different target resource for a slot of the round. Other embodiments are described and claimed.Type: ApplicationFiled: May 14, 2007Publication date: November 20, 2008Inventors: Brian Hoang, Khee Wooi Lee