Abstract: A semiconductor device includes: a first stack structure; a second stack structure; a slit insulating layer located between the first stack structure and the second stack structure, the slit insulating layer extending in a first direction; a conductive plug located between the first stack structure and the second stack structure, the conductive plug including a first protrusion part protruding to the inside of the slit insulating layer; and an insulating spacer surrounding a sidewall of the conductive plug.

Abstract: A method for fabricating a semiconductor device includes forming a through-hole penetrating through an alternating stack pattern and forming a gap-fill layer, wherein a sacrificial gap-fill layer of the gap-fill layer fills the through-hole. The method also includes forming a mask layer over the alternating stack pattern and over the gap-fill layer, wherein the mask layer includes a self-aligned opening overlapping the filled through-hole and overlapping a portion of an uppermost material layer of the alternating stack pattern adjacent to the filled through-hole. The method further includes forming a first contact hole through the alternating stack pattern by performing a single etch using both the mask layer and the portion of the uppermost material layer as etch barriers to remove, through the self-aligned opening, the sacrificial gap-fill layer filling the through-hole.

Abstract: A method for fabricating a semiconductor device includes forming a through-hole penetrating through an alternating stack pattern and forming a gap-fill layer, wherein a sacrificial gap-fill layer of the gap-fill layer fills the through-hole. The method also includes forming a mask layer over the alternating stack pattern and over the gap-fill layer, wherein the mask layer includes a self-aligned opening overlapping the filled through-hole and overlapping a portion of an uppermost material layer of the alternating stack pattern adjacent to the filled through-hole. The method further includes forming a first contact hole through the alternating stack pattern by performing a single etch using both the mask layer and the portion of the uppermost material layer as etch barriers to remove, through the self-aligned opening, the sacrificial gap-fill layer filling the through-hole.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure; a slit insulating layer located between the first stack structure and the second stack structure, the slit insulating layer extending in a first direction; a conductive plug located between the first stack structure and the second stack structure, the conductive plug including a first protrusion part protruding to the inside of the slit insulating layer; and an insulating spacer surrounding a sidewall of the conductive plug.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure; a slit insulating layer located between the first stack structure and the second stack structure, the slit insulating layer extending in a first direction; a conductive plug located between the first stack structure and the second stack structure, the conductive plug including a first protrusion part protruding to the inside of the slit insulating layer; and an insulating spacer surrounding a sidewall of the conductive plug.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure; a slit insulating layer located between the first stack structure and the second stack structure, the slit insulating layer extending in a first direction; a conductive plug located between the first stack structure and the second stack structure, the conductive plug including a first protrusion part protruding to the inside of the slit insulating layer; and an insulating spacer surrounding a sidewall of the conductive plug.

Abstract: A method for fabricating a semiconductor device includes forming a through-hole penetrating through an alternating stack pattern and forming a gap-fill layer, wherein a sacrificial gap-fill layer of the gap-fill layer fills the through-hole. The method also includes forming a mask layer over the alternating stack pattern and over the gap-fill layer, wherein the mask layer includes a self-aligned opening overlapping the filled through-hole and overlapping a portion of an uppermost material layer of the alternating stack pattern adjacent to the filled through-hole. The method further includes forming a first contact hole through the alternating stack pattern by performing a single etch using both the mask layer and the portion of the uppermost material layer as etch barriers to remove, through the self-aligned opening, the sacrificial gap-fill layer filling the through-hole.

Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over the first gate electrode layer, forming a first channel hole that exposes the first sacrificial layer by penetrating through the stacked structure, forming a second channel hole by removing the exposed first sacrificial layer, forming an oxide layer by oxidizing a surface of the first gate electrode layer exposed through the first and second channel holes, forming a channel layer in the first and second channel holes, and forming second gate electrode layers in spaces from which the second sacrificial layers are removed, wherein a memory layer is interposed between the channel layer and the second gate electrode layer.

Abstract: A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines formed in the second insulating layer, and a first air gap disposed between the first insulating layer and the second insulating layer to surround a lower part of the interconnection lines.

Abstract: A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines formed in the second insulating layer, and a first air gap disposed between the first insulating layer and the second insulating layer to surround a lower part of the interconnection lines.

Abstract: A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines formed in the second insulating layer, and a first air gap disposed between the first insulating layer and the second insulating layer to surround a lower part of the interconnection lines.

Abstract: A method of manufacturing a semiconductor device includes forming a sacrificial pattern, forming a first stacked structure including first material layers and second material layers alternately stacked on the sacrificial pattern, forming first semiconductor patterns passing through the first stacked structure and dielectric multi-layers surrounding the first semiconductor patterns, forming a slit passing through the first stacked structure and exposing the sacrificial pattern, forming a spacer on an inner wall of the slit, forming a first opening by removing the sacrificial pattern through the slit, forming a second opening by partially removing the dielectric multi-layers through the first opening to expose lower portions of the first semiconductor patterns, and forming a connection pattern in contact with the first semiconductor patterns in the first and second openings.

Abstract: A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines formed in the second insulating layer, and a first air gap disposed between the first insulating layer and the second insulating layer to surround a lower part of the interconnection lines.

Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over the first gate electrode layer, forming a first channel hole that exposes the first sacrificial layer by penetrating through the stacked structure, forming a second channel hole by removing the exposed first sacrificial layer, forming an oxide layer by oxidizing a surface of the first gate electrode layer exposed through the first and second channel holes, forming a channel layer in the first and second channel holes, and forming second gate electrode layers in spaces from which the second sacrificial layers are removed, wherein a memory layer is interposed between the channel layer and the second gate electrode layer.

Abstract: A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to be measured even in the SAFG scheme. Contacts for resistivity measurement are directly connected to the resistivity measurement floating gate. Therefore, variation in resistivity measurement values, which is incurred by the parasitic interface, can be reduced.

Abstract: A method of manufacturing a semiconductor device in a MLM process to reduce compression stress of a metal line or a HDP oxide film, and to reduce compression stress in a subsequent metal line thermal treatment process. It is thus possible to reduce generation of a crack caused by compression stress. Further, by obviating a heterogeneous interface becoming a cause of a crack and stabilizing the interface of an unstable TEOS oxide film, generation of a crack in a semiconductor device can be reduced.

Abstract: A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to be measured even in the SAFG scheme. Contacts for resistivity measurement are directly connected to the resistivity measurement floating gate. Therefore, variation in resistivity measurement values, which is incurred by the parasitic interface, can be reduced.

Abstract: A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to be measured even in the SAFG scheme. Contacts for resistivity measurement are directly connected to the resistivity measurement floating gate. Therefore, variation in resistivity measurement values, which is incurred by the parasitic interface, can be reduced.

Abstract: A method for forming a metal pattern in a semiconductor device includes preparing a semi-finished substrate with a metal layer for use as a metal pattern, performing a cleaning process inducing oxidation over an upper surface of the metal layer to form an anti-scattering reflection layer over the upper surface of the metal layer, forming a photoresist pattern over the anti-scattering reflection layer, and etching the anti-scattering reflection layer and the metal layer exposed by the photoresist pattern to form the metal pattern.

Abstract: Disclosed is a method for manufacturing slurry capable of stably polishing polycrystal silicon without change of surface roughness in a Chemical Mechanical Polishing process. The disclosed includes hydroxide ion added to the slurry in order to decrease acidity and increase alkalinity.