Abstract: An erasable, programmable ROM (10) with three redundant bit-cell arrays (10A, 10B, 10C) includes an error-flagging circuit (30) that detects bit-cell failures and provides notification of each such failure. The error-flagging circuit (30) includes a plurality of XOR gates (32), each receiving the corresponding redundant data bits for one of the bits of an addressed byte, and a NOR gate (36) which receives the outputs from each of the XOR gates (32). Each XOR gate detects when the logic states for the input redundant bits are not identical, indicating a bit-cell failure has occurred, and provides a corresponding logic state output. The NOR gate (36) detects when any of the XOR gates (32) has indicated a bit-cell failure, and generates an error-flag output providing notification of such failure.

Abstract: The device refreshes the cells of an array of dynamic memory cells a row at a time during precharging of the bit or column lines. Normal access to read or write to the cells also refreshes them. Refresh circuits connect to the row line between the row address decoder and the cells, and include shift register stages connected to the row lines. A bit of one sense shifting through the stages indicates the row to be refreshed and a refresh signal connected to the stages times the refresh during the precharge. Using multiple, sequential refresh signals refreshes alternating rows of the cells.

Abstract: A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type is disclosed. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device therein which operates relatively independently from the host CPU, and which is coupled to the main memory by the system bus, includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter.

Abstract: A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU, is coupled to the main memory by the system bus and includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus.