Patents by Inventor Ki-Sang Kang
Ki-Sang Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7886206Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.Type: GrantFiled: March 31, 2009Date of Patent: February 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Je-Young Park, Ki-Sang Kang
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Patent number: 7838790Abstract: A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.Type: GrantFiled: November 9, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-goo Kang, Jun-ho Lee, Ki-sang Kang, Hyun-seop Shim, Do-young Kam, Jae-il Lee, Ju-il Kang
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Patent number: 7633288Abstract: Example embodiments may provide a method of testing semiconductor devices by identifying units of lots and a test tray such that a plurality of lots having semiconductor devices may be continuously tested by a handler. Example embodiments may also provide a handler used to test the semiconductor devices.Type: GrantFiled: September 27, 2006Date of Patent: December 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Ae-Yong Chung, Eun-Seok Lee, Ki-Sang Kang, Kyeong-Seon Shin
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Publication number: 20090206856Abstract: The present disclosure relates to a wafer burn-in system having a device cooling a probe card and thereby restraining heat accumulation in the probe card. The disclosed wafer burn-in system includes a probe station and a tester. The probe station includes a burn-in chamber, a probe head, and a wafer stage. The probe head has a probe card installed on the lower surface of the probe head. A cooling device restrains heat accumulation in the probe card, e.g., by generating airflow around the probe card. The wafer stage of the burn-in chamber fixes a wafer loaded on the upper surface of the wafer stage and elevates the wafer for contact with the probe card. The tester connects to the probe station through a general purpose interface bus (GPIB) to convey test signals to and from the probe head, and to control operation of the cooling device. The tester activates the cooling device, e.g.Type: ApplicationFiled: April 20, 2009Publication date: August 20, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Hyun NAM, Ki-Sang KANG, Gi-Bum KOO, Hoon-Jung KIM, In-Seok HWANG
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Publication number: 20090199059Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.Type: ApplicationFiled: March 31, 2009Publication date: August 6, 2009Inventors: Je-Young Park, Ki-Sang Kang
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Patent number: 7554349Abstract: A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.Type: GrantFiled: March 29, 2007Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-goo Kang, Jun-ho Lee, Ki-sang Kang, Hyun-seop Shim, Do-young Kam, Jae-il Lee, Ju-il Kang
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Patent number: 7533310Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.Type: GrantFiled: December 19, 2006Date of Patent: May 12, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Je-Young Park, Ki-Sang Kang
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Publication number: 20080110809Abstract: A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.Type: ApplicationFiled: November 9, 2007Publication date: May 15, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Seong-goo Kang, Jun-ho Lee, Ki-sang Kang, Hyun-seop Shim, Do-young Kam, Jae-il Lee, Ju-il Kang
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Publication number: 20070236235Abstract: A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.Type: ApplicationFiled: March 29, 2007Publication date: October 11, 2007Inventors: Seong-goo Kang, Jun-ho Lee, Ki-sang Kang, Hyun-seop Shim, Do-young Kam, Jae-il Lee, Ju-il Kang
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Publication number: 20070162794Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.Type: ApplicationFiled: December 19, 2006Publication date: July 12, 2007Inventors: Je-Young Park, Ki-Sang Kang
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Publication number: 20070075719Abstract: Example embodiments may provide a method of testing semiconductor devices by identifying units of lots and a test tray such that a plurality of lots having semiconductor devices may be continuously tested by a handler. Example embodiments may also provide a handler used to test the semiconductor devices.Type: ApplicationFiled: September 27, 2006Publication date: April 5, 2007Inventors: Ae-Yong Chung, Eun-Seok Lee, Ki-Sang Kang, Kyeong-Seon Shin
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Patent number: 7153087Abstract: A centering unit comprises a plate, centering mechanism, link mechanism, and cylinder mechanism. The plate vertically divides the interior of a frame. The support table is located substantially on the center of the plate. The centering mechanism can center each wafer on the support table. Centering plates of the centering mechanism are located on either side of the support table and have engaging surfaces and that extend along the outer peripheral surface of the wafer. The link mechanism and the cylinder mechanism serve to extend and contract the space between the centering plates.Type: GrantFiled: January 27, 2003Date of Patent: December 26, 2006Assignees: Samsung Electronics Co., Ltd., Tokyo Electron LimitedInventors: Ki Sang Kang, Shuji Akiyama, Hiroki Hosaka
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Patent number: 7103493Abstract: Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During functional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.Type: GrantFiled: May 24, 2004Date of Patent: September 5, 2006Assignee: Samsung Electronics Co., LTDInventors: Ki-Sang Kang, Tsutomu Akiyama, Je-Young Park
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Publication number: 20060170437Abstract: A probe card for that may be used to test a plurality of semiconductor chips formed on a wafer. The probe card may include a substrate; a plurality of probe blocks that form a pattern corresponding to the pattern formed by the plurality of semiconductor chips formed on the wafer; and a plurality of probe needles formed in the probe blocks and arranged in a pattern corresponding to a plurality of pads formed in the plurality of semiconductor chips. The use of the probe card may decrease the testing time for the wafer.Type: ApplicationFiled: January 12, 2006Publication date: August 3, 2006Inventors: Sang-Kyu Yoo, Ki-Sang Kang, Hoon-Jung Kim, Sung-Mo Kang, Chang-Hyun Cho
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Publication number: 20060152239Abstract: The present disclosure relates to a wafer burn-in system having a device cooling a probe card and thereby restraining heat accumulation in the probe card. The disclosed wafer burn-in system includes a probe station and a tester. The probe station includes a burn-in chamber, a probe head, and a wafer stage. The probe head has a probe card installed on the lower surface of the probe head. A cooling device restrains heat accumulation in the probe card, e.g., by generating airflow around the probe card. The wafer stage of the burn-in chamber fixes a wafer loaded on the upper surface of the wafer stage and elevates the wafer for contact with the probe card. The tester connects to the probe station through a general purpose interface bus (GPIB) to convey test signals to and from the probe head, and to control operation of the cooling device. The tester activates the cooling device, e.g.Type: ApplicationFiled: January 4, 2006Publication date: July 13, 2006Inventors: Jung-Hyun Nam, Ki-Sang Kang, Gi-Bum Koo, Hoon-Jung Kim, In-Seok Hwang
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Patent number: 6972612Abstract: An integrated circuit of a semiconductor device has a chip malfunction controlling circuit embedded in a chip. The circuit comprises a fusing part, to which a cutting will be made in the manufacturing process according to the result of the discrimination of a defect in a chip, with one end thereof being connected to a first power terminal. A signal generating part is connected to the other end of the fusing part, and to a second power terminal. The signal generating part generates a discrimination signal of discriminating whether the chip is defective or not, by whether the fusing part has been cut or not. The discrimination signal is supplied to at least one internal function circuit, and inhibits its operation if the fusing part has been cut. Furthermore, the chip malfunction controlling method comprises generating a discrimination signal that has a first state if a test fuse has been cut and a second state if the test fuse has not been cut.Type: GrantFiled: October 21, 2002Date of Patent: December 6, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Seok Kang, Kyeong-Seon Shin, Ki-Sang Kang
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Publication number: 20050043912Abstract: Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During funtional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.Type: ApplicationFiled: May 24, 2004Publication date: February 24, 2005Inventors: Ki-Sang Kang, Tsutomu Akiyama, Je-Young Park
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Patent number: 6642729Abstract: A semiconductor integrated circuit wafer tester includes a supporting plate on which a semiconductor wafer may be positioned and a tester head having a circular top plate installed a predetermined distance away from the supporting plate, wherein a probe card in the tester head that includes a circular printed circuit board having a diameter of at least 400 mm (15.75 inches) that is connected to the top plate and having a plurality of probe units formed on the printed circuit board allows electrical parameters of multiple chips formed on the semiconductor wafer to be measured simultaneously.Type: GrantFiled: December 28, 2001Date of Patent: November 4, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-sang Kang, Sung-mo Kang
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Patent number: 6625766Abstract: A test method of a tester of a semiconductor memory device which includes recording a test pattern into the semiconductor memory device, reading the recorded test pattern to compare with a expected pattern, detecting information on a defect of the semiconductor memory device with a result of the comparison and interpreting the information on the defect of the semiconductor memory device, the method comprising the steps of: setting up minimum and maximum values relevant to a desired capacity of the semiconductor memory device to be tested; counting up from the preset minimum to the preset maximum values; generating a carry signal by comparing the preset maximum value with the counted value when the counted value gets to the preset maximum value; and resetting a value to be counted if the carry signal is generated, to thereby generate addresses of the semiconductor memory device, and a tester of the semiconductor memory device comprising: minimum and maximum address registering means for saving minimum and maxiType: GrantFiled: February 24, 2000Date of Patent: September 23, 2003Assignee: Samsung Electronics Co, Ltd.Inventors: Se-Jang Oh, Ki-Sang Kang
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Publication number: 20030160401Abstract: A centering unit comprises a plate, centering mechanism, link mechanism, and cylinder mechanism. The plate vertically divides the interior of a frame. The support table is located substantially on the center of the plate. The centering mechanism can center each wafer on the support table. Centering plates of the centering mechanism are located on either side of the support table and have engaging surfaces and that extend along the outer peripheral surface of the wafer. The link mechanism and the cylinder mechanism serve to extend and contract the space between the centering plates.Type: ApplicationFiled: January 27, 2003Publication date: August 28, 2003Inventors: Ki Sang Kang, Shuji Akiyama, Hiroki Hosaka