Patents by Inventor Ki-Sang Kang

Ki-Sang Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11544102
    Abstract: A method for batch processing for a plurality of individual transactions includes generating a batch transaction by aggregating at least some of the plurality of individual transactions according to a setting value of a batch size, and processing the batch transaction via a blockchain network. The generation of the batch transaction includes adjusting the setting value of the batch size based on a monitoring result for a transaction processing status, and generating the batch transaction according to the adjusted setting value.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: January 3, 2023
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Kyu Sang Lee, Chang Suk Yoon, Sang Jun Kang, Ki Woon Sung
  • Publication number: 20220403517
    Abstract: Provided is an apparatus for treating a substrate. The apparatus for treating the substrate includes a chamber having an inner space, a support unit configured to support the substrate in the inner space, a gas supply tube configured to supply a gas onto the substrate supported on the support unit, a gas exhaust tube configured to exhaust the gas from the inner space, and a gas block connected to the gas supply tube and the gas exhaust tube and provided above the chamber.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 22, 2022
    Applicant: SEMES CO., LTD.
    Inventors: Ki Sang EUM, Woo Ram LEE, Jong Wha KANG, Dong Woon PARK
  • Patent number: 7886206
    Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Young Park, Ki-Sang Kang
  • Patent number: 7838790
    Abstract: A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: November 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-goo Kang, Jun-ho Lee, Ki-sang Kang, Hyun-seop Shim, Do-young Kam, Jae-il Lee, Ju-il Kang
  • Patent number: 7633288
    Abstract: Example embodiments may provide a method of testing semiconductor devices by identifying units of lots and a test tray such that a plurality of lots having semiconductor devices may be continuously tested by a handler. Example embodiments may also provide a handler used to test the semiconductor devices.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: December 15, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-Yong Chung, Eun-Seok Lee, Ki-Sang Kang, Kyeong-Seon Shin
  • Publication number: 20090206856
    Abstract: The present disclosure relates to a wafer burn-in system having a device cooling a probe card and thereby restraining heat accumulation in the probe card. The disclosed wafer burn-in system includes a probe station and a tester. The probe station includes a burn-in chamber, a probe head, and a wafer stage. The probe head has a probe card installed on the lower surface of the probe head. A cooling device restrains heat accumulation in the probe card, e.g., by generating airflow around the probe card. The wafer stage of the burn-in chamber fixes a wafer loaded on the upper surface of the wafer stage and elevates the wafer for contact with the probe card. The tester connects to the probe station through a general purpose interface bus (GPIB) to convey test signals to and from the probe head, and to control operation of the cooling device. The tester activates the cooling device, e.g.
    Type: Application
    Filed: April 20, 2009
    Publication date: August 20, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hyun NAM, Ki-Sang KANG, Gi-Bum KOO, Hoon-Jung KIM, In-Seok HWANG
  • Publication number: 20090199059
    Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
    Type: Application
    Filed: March 31, 2009
    Publication date: August 6, 2009
    Inventors: Je-Young Park, Ki-Sang Kang
  • Patent number: 7554349
    Abstract: A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: June 30, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-goo Kang, Jun-ho Lee, Ki-sang Kang, Hyun-seop Shim, Do-young Kam, Jae-il Lee, Ju-il Kang
  • Patent number: 7533310
    Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Young Park, Ki-Sang Kang
  • Publication number: 20080110809
    Abstract: A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.
    Type: Application
    Filed: November 9, 2007
    Publication date: May 15, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seong-goo Kang, Jun-ho Lee, Ki-sang Kang, Hyun-seop Shim, Do-young Kam, Jae-il Lee, Ju-il Kang
  • Publication number: 20070236235
    Abstract: A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 11, 2007
    Inventors: Seong-goo Kang, Jun-ho Lee, Ki-sang Kang, Hyun-seop Shim, Do-young Kam, Jae-il Lee, Ju-il Kang
  • Publication number: 20070162794
    Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
    Type: Application
    Filed: December 19, 2006
    Publication date: July 12, 2007
    Inventors: Je-Young Park, Ki-Sang Kang
  • Publication number: 20070075719
    Abstract: Example embodiments may provide a method of testing semiconductor devices by identifying units of lots and a test tray such that a plurality of lots having semiconductor devices may be continuously tested by a handler. Example embodiments may also provide a handler used to test the semiconductor devices.
    Type: Application
    Filed: September 27, 2006
    Publication date: April 5, 2007
    Inventors: Ae-Yong Chung, Eun-Seok Lee, Ki-Sang Kang, Kyeong-Seon Shin
  • Patent number: 7153087
    Abstract: A centering unit comprises a plate, centering mechanism, link mechanism, and cylinder mechanism. The plate vertically divides the interior of a frame. The support table is located substantially on the center of the plate. The centering mechanism can center each wafer on the support table. Centering plates of the centering mechanism are located on either side of the support table and have engaging surfaces and that extend along the outer peripheral surface of the wafer. The link mechanism and the cylinder mechanism serve to extend and contract the space between the centering plates.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: December 26, 2006
    Assignees: Samsung Electronics Co., Ltd., Tokyo Electron Limited
    Inventors: Ki Sang Kang, Shuji Akiyama, Hiroki Hosaka
  • Patent number: 7103493
    Abstract: Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During functional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: September 5, 2006
    Assignee: Samsung Electronics Co., LTD
    Inventors: Ki-Sang Kang, Tsutomu Akiyama, Je-Young Park
  • Publication number: 20060170437
    Abstract: A probe card for that may be used to test a plurality of semiconductor chips formed on a wafer. The probe card may include a substrate; a plurality of probe blocks that form a pattern corresponding to the pattern formed by the plurality of semiconductor chips formed on the wafer; and a plurality of probe needles formed in the probe blocks and arranged in a pattern corresponding to a plurality of pads formed in the plurality of semiconductor chips. The use of the probe card may decrease the testing time for the wafer.
    Type: Application
    Filed: January 12, 2006
    Publication date: August 3, 2006
    Inventors: Sang-Kyu Yoo, Ki-Sang Kang, Hoon-Jung Kim, Sung-Mo Kang, Chang-Hyun Cho
  • Publication number: 20060152239
    Abstract: The present disclosure relates to a wafer burn-in system having a device cooling a probe card and thereby restraining heat accumulation in the probe card. The disclosed wafer burn-in system includes a probe station and a tester. The probe station includes a burn-in chamber, a probe head, and a wafer stage. The probe head has a probe card installed on the lower surface of the probe head. A cooling device restrains heat accumulation in the probe card, e.g., by generating airflow around the probe card. The wafer stage of the burn-in chamber fixes a wafer loaded on the upper surface of the wafer stage and elevates the wafer for contact with the probe card. The tester connects to the probe station through a general purpose interface bus (GPIB) to convey test signals to and from the probe head, and to control operation of the cooling device. The tester activates the cooling device, e.g.
    Type: Application
    Filed: January 4, 2006
    Publication date: July 13, 2006
    Inventors: Jung-Hyun Nam, Ki-Sang Kang, Gi-Bum Koo, Hoon-Jung Kim, In-Seok Hwang
  • Patent number: 6972612
    Abstract: An integrated circuit of a semiconductor device has a chip malfunction controlling circuit embedded in a chip. The circuit comprises a fusing part, to which a cutting will be made in the manufacturing process according to the result of the discrimination of a defect in a chip, with one end thereof being connected to a first power terminal. A signal generating part is connected to the other end of the fusing part, and to a second power terminal. The signal generating part generates a discrimination signal of discriminating whether the chip is defective or not, by whether the fusing part has been cut or not. The discrimination signal is supplied to at least one internal function circuit, and inhibits its operation if the fusing part has been cut. Furthermore, the chip malfunction controlling method comprises generating a discrimination signal that has a first state if a test fuse has been cut and a second state if the test fuse has not been cut.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: December 6, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Seok Kang, Kyeong-Seon Shin, Ki-Sang Kang
  • Publication number: 20050043912
    Abstract: Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During funtional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.
    Type: Application
    Filed: May 24, 2004
    Publication date: February 24, 2005
    Inventors: Ki-Sang Kang, Tsutomu Akiyama, Je-Young Park
  • Patent number: 6642729
    Abstract: A semiconductor integrated circuit wafer tester includes a supporting plate on which a semiconductor wafer may be positioned and a tester head having a circular top plate installed a predetermined distance away from the supporting plate, wherein a probe card in the tester head that includes a circular printed circuit board having a diameter of at least 400 mm (15.75 inches) that is connected to the top plate and having a plurality of probe units formed on the printed circuit board allows electrical parameters of multiple chips formed on the semiconductor wafer to be measured simultaneously.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: November 4, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-sang Kang, Sung-mo Kang