Abstract: Disclosed are a system and method for automatically evaluating an essay. The system includes a structure analysis module configured to divide learning data and learner essay text in a predetermined structure analysis unit, generate structure tagging information for each structure analysis unit, and structure the learning data and the learner essay text by attaching the structure tagging information to the learning data and the learner essay text, a learning module configured to generate an essay evaluation model through learning by using essay text that is included in the structured learning data and the structure tagging information as an input value and using an evaluation score that is included in the structured learning data as a label, and an evaluation module configured to generate essay evaluation results using the essay evaluation model.

Abstract: An automated driving system of a vehicle includes a driver monitoring unit configured to perform at least one of monitoring a gaze of a driver and determining a position of a hand of the driver, an automated-driving-level switching unit configured to determine whether a transition of a driving control over the vehicle is required based on whether driving environment of the vehicle has changed during the vehicle being driven under control of the automated driving system, and determine an automated driving level to be switched based on a driver monitoring result obtained by the drive monitoring unit, and an automated driving control unit configured to control the vehicle according to the automated driving level.

Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.

Abstract: A sterilizing device includes a pipe having an inlet and an outlet and allowing fluid to move therethrough and a light source provided on one side of the pipe and providing light to the fluid. At least a portion of the pipe is provided in a spiral shape and the inlet and/or the outlet are arranged in a light emitting region.

Abstract: An embodiment of the present disclosure discloses a method of process variation compensating through activation value adjustment of an analog binarized neural network circuit that may recover a decrease in recognition rate performance up to an almost perfect level, even if a binarized neural network is implemented as an analog circuit such that recognition rate performance is decreased due to process variation.

Abstract: A method of processing data including receiving data to be stored in a first group of cache banks from among a plurality of cache banks corresponding to a plurality of cores. The method further includes partitioning the received data and transmitting the partitioned data to the first group of cache banks according to a write intensity of the received data, and storing a portion of the transmitted data in a first cache bank from among the first group of cache banks.

Abstract: A method of processing data including receiving data to be stored in a first group of cache banks from among a plurality of cache banks corresponding to a plurality of cores. The method further includes partitioning the received data and transmitting the partitioned data to the first group of cache banks according to a write intensity of the received data, and storing a portion of the transmitted data in a first cache bank from among the first group of cache banks.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: The present invention relates to a coarse-grained reconfigurable array, comprising: at least one processor; a processing element array including a plurality of processing elements, and a configuration cache where commands being executed by the processing elements are saved; and a plurality of memory units forming a one-to-one mapping with the processor and the processing element array. The coarse-grained reconfigurable array further comprises a central memory performing data communications between the processor and the processing element array by switching the one-to-one mapping such that when the processor transfers data from/to a main memory to/from a frame buffer, a significant bottleneck phenomenon that may occur due to the limited bandwidth and latency of a system bus can be improved.

Abstract: Disclosed is a nanoparticulate complex comprising an artificial phosphate receptor of formula (I): P-[L-[-N(CH2-2-pyridyl)2]]p.pZN2+ (I) wherein P represents a nanoparticulate substrate, L represents a linking group, and p is an integer of ?1. Also disclosed are a method for silencing a gene in a cancer patient in need thereof, a method for treating or preventing cancer in a patient in need thereof, and a method for targeting a cell in cancer treatment comprising use of the nanoparticulate complex, for example, a DPA/Zn-functionalized nanoparticulate complex.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: The present invention relates to a coarse-grained reconfigurable array, comprising: at least one processor; a processing element array including a plurality of processing elements, and a configuration cache where commands being executed by the processing elements are saved; and a plurality of memory units forming a one-to-one mapping with the processor and the processing element array. The coarse-grained reconfigurable array further comprises a central memory performing data communications between the processor and the processing element array by switching the one-to-one mapping such that when the processor transfers data from/to a main memory to/from a frame buffer, a significant bottleneck phenomenon that may occur due to the limited bandwidth and latency of a system bus can be improved.

Abstract: Disclosed is a network-on-chip system including an active memory processor for processing increased communication latency by multiple processors and memories. The network-on-chip system includes a plurality of processing elements that request to perform an active memory operation for a predetermined operation from a shared memory to reduce access latency of the shared memory, and an active memory processor connected to the processing elements through a network, storing codes for processing custom transaction in request to the active memory operation, performing an operation addresses or data stored in a shared cache memory or the shared memory based on the codes and transmitting the performed operation result to the processing elements.

Abstract: Techniques, apparatus and systems are described for performing variable length decoding. In one aspect, a variable length decoding apparatus includes a first computation unit to determine whether a symbol corresponding to an input data is included in an upper group or a lower group of a variable length code tree. Responsive to the determination, when the symbol corresponding to the input data is included in the lower group, the first computation unit detects look-up table information corresponding to a subgroup that includes the symbol corresponding to the input data within the lower group that includes multiple subgroups. The variable length decoding apparatus includes a second computation unit to detect the symbol corresponding to the input data by searching a look-up table corresponding to the look-up table information when the look-up table information is received from the first computation unit.

Abstract: A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.

Abstract: Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing element includes an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU.

Abstract: Techniques, apparatus and systems are described for performing variable length decoding. In one aspect, a variable length decoding apparatus includes a first computation unit to determine whether a symbol corresponding to an input data is included in an upper group or a lower group of a variable length code tree. Responsive to the determination, when the symbol corresponding to the input data is included in the lower group, the first computation unit detects look-up table information corresponding to a subgroup that includes the symbol corresponding to the input data within the lower group that includes multiple subgroups. The variable length decoding apparatus includes a second computation unit to detect the symbol corresponding to the input data by searching a look-up table corresponding to the look-up table information when the look-up table information is received from the first computation unit.

Abstract: Provided are a method and apparatus for sharing a memory of a multi-codec. For each of a plurality of codecs, the method and apparatus cluster a variable length code tree into a plurality of groups whereby a level difference between symbols in each group of the plurality of groups is less than a predetermined value, wherein the variable length code tree corresponds to at least one of variable length code tables for each of the plurality of codecs, refer to maximum levels of the symbols in each group of the plurality of groups, and determine a storage capacity of an internal memory shared between the variable length code tables for the plurality of codecs.