Patents by Inventor Kian Chai Lee
Kian Chai Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8084846Abstract: A semiconductor device assembly or package includes at least one semiconductor device that is positioned adjacent to floating leads. Such an assembly or package may include at least two semiconductor devices that face opposite directions from one another, with each being oriented such that bond pads thereof are at an opposite side of the assembly or package from bond pads of the other. Alternatively, an assembly or package may include a lead assembly with an internal portion, including one or more floating leads, and an external portion that are in planes that are offset relative to one another. Methods for designing lead frames, assemblies, and packages are also disclosed, as are assembly and packaging methods.Type: GrantFiled: November 29, 2006Date of Patent: December 27, 2011Assignee: Micron Technology, Inc.Inventors: Teck Kheng Lee, Kian Chai Lee, Vanessa Chong Hui Van
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Patent number: 7915718Abstract: A method and apparatus for increasing the integrated circuit density in a flip-chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second surface thereof, wherein the recesses are arranged in a plurality of recess patterns. The interposer substrate also provides enhanced accessibility for test probes for electrical testing of the resulting flip-chip semiconductor device assembly.Type: GrantFiled: May 17, 2002Date of Patent: March 29, 2011Assignee: Micron Technology, Inc.Inventors: Teck Kheng Lee, Wuu Yean Tay, Kian Chai Lee
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Publication number: 20080122072Abstract: A semiconductor device assembly or package includes at least one semiconductor device that is positioned adjacent to floating leads. Such an assembly or package may include at least two semiconductor devices that face opposite directions from one another, with each being oriented such that bond pads thereof are at an opposite side of the assembly from bond pads of the other. Alternatively, an assembly or package may include a lead assembly with an internal portion, including one or more floating leads, and an external portion that are in planes that are offset relative to one another. Methods for designing lead frames, assemblies, and packages are also disclosed, as are assembly and packaging methods.Type: ApplicationFiled: November 29, 2006Publication date: May 29, 2008Inventors: Teck Kheng Lee, Kian Chai Lee, Vanessa Chong Hui Van
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Patent number: 7368391Abstract: A method for designing a carrier substrate includes configuring at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The method may also include configuring the carrier substrate to include one or more recessed areas that laterally surround at least a portion of the die-attach location to receive excess adhesive.Type: GrantFiled: August 29, 2005Date of Patent: May 6, 2008Assignee: Micron Technology, Inc.Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Pour Poh
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Patent number: 7320933Abstract: An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.Type: GrantFiled: April 22, 2004Date of Patent: January 22, 2008Assignee: Micron Technology, Inc.Inventors: Teck Kheng Lee, Kian Chai Lee, Sian Yong Khoo
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Patent number: 7112048Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.Type: GrantFiled: April 8, 2003Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
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Patent number: 7061124Abstract: A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The solder may be positioned or formed on the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive excess adhesive.Type: GrantFiled: September 7, 2004Date of Patent: June 13, 2006Assignee: Micron Technology, Inc.Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Poh Pour
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Patent number: 7018871Abstract: A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.Type: GrantFiled: August 18, 2003Date of Patent: March 28, 2006Assignee: Micron Technology, Inc.Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Pour Poh
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Patent number: 7005316Abstract: A method and apparatus for assembling semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the interposer substrate and wire bonded to terminals on the opposing substrate surface through an opening in the interposer substrate. Two interposer substrates are placed together with die-carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.Type: GrantFiled: December 31, 2002Date of Patent: February 28, 2006Assignee: Micron Technology, Inc.Inventors: Teck Kheng Lee, Kian Chai Lee
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Publication number: 20040198033Abstract: An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.Type: ApplicationFiled: April 22, 2004Publication date: October 7, 2004Inventors: Teck Kheng Lee, Kian Chai Lee, Sian Yong Khoo
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Patent number: 6787923Abstract: A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.Type: GrantFiled: April 10, 2002Date of Patent: September 7, 2004Assignee: Micron Technology, Inc.Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Pour Poh
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Patent number: 6787917Abstract: An electronic device package having semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the interposer substrate and wire bonded to terminals on the opposing substrate surface through an opening in the interposer substrate. Two interposer substrates are placed together with die-carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.Type: GrantFiled: March 12, 2003Date of Patent: September 7, 2004Assignee: Micron Technology, Inc.Inventors: Teck Kheng Lee, Kian Chai Lee
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Publication number: 20040077109Abstract: A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.Type: ApplicationFiled: August 18, 2003Publication date: April 22, 2004Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Poh Pour
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Patent number: 6720666Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.Type: GrantFiled: April 8, 2003Date of Patent: April 13, 2004Assignee: Micron Technology, Inc.Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
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Publication number: 20040036170Abstract: An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.Type: ApplicationFiled: August 20, 2002Publication date: February 26, 2004Inventors: Teck Kheng Lee, Kian Chai Lee, Sian Yong Khoo
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Patent number: 6692987Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.Type: GrantFiled: February 5, 2002Date of Patent: February 17, 2004Assignee: Micron Technology, Inc.Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
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Patent number: 6656769Abstract: A method and apparatus for distributing a mold material in a mold for packaging microelectronic devices. In one embodiment, the microelectronic devices are placed on a substrate and the substrate is at least partially enclosed by the device region of a mold cavity. A mold material is passed along a flow axis through at least one entrance port into an intermediate region of the mold. The mold material is then passed from the intermediate region into the device region through a single opening spaced apart from and positioned between the entrance port and the microelectronic device. The single opening has a flow area transverse to the flow axis smaller than a flow area immediately upstream of the single opening to restrict the flow through the single opening. The mold material can accordingly form a uniform leading edge as it exits the opening and before it impinges on the microelectronic device.Type: GrantFiled: May 8, 2001Date of Patent: December 2, 2003Assignee: Micron Technology, Inc.Inventors: Kian Chai Lee, Teoh Bee Yong Tim, Vijendran M, Lien Wah Choong
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Publication number: 20030211659Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.Type: ApplicationFiled: April 8, 2003Publication date: November 13, 2003Applicant: Micron Technology, Inc.Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
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Publication number: 20030211660Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.Type: ApplicationFiled: April 8, 2003Publication date: November 13, 2003Applicant: Micron Technology, Inc.Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
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Publication number: 20030193092Abstract: A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.Type: ApplicationFiled: April 10, 2002Publication date: October 16, 2003Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Pour Poh
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Patent number: 4784274Abstract: This bill device is constituted of a relatively elongated casing. A bill insertion slit is formed substantially in the center of this casing in its longitudinal direction. A first U-shaped bill conveying passage communicating with the bill insertion slit is provided in one half of the casing and a second U-shaped bill conveying passage communicating with this first U-shaped bill conveying passage is provided in another half of the casing. A bill discrimination section is disposed in the former half of the first U-shaped bill conveying passage and a bill accumulating device is disposed in the latter half of the second bill conveying passage such that a plurality of bills after discrimination are retained in the two U-shaped bill conveying passages.Type: GrantFiled: July 13, 1987Date of Patent: November 15, 1988Assignee: Kabushiki Kaisha Nippon CoincoInventors: Yoshikazu Mori, Susumu Kozima, Masayuki Watabe, Hideaki Onda, Shigeru Yasuda