Abstract: Example implementations described herein involve a media adaptor configured to provide electrical/optical and optical/electrical conversion for a multi-mode waveguide (MMWG) interconnect, the media adaptor involving one or more ball grid arrays; and a tail-cut fiber array block (tcFAB) connected to a first array of photodiodes and a second array of laser diodes from direct optical wire (DOW) bonding.

Abstract: Example implementations described herein are directed to an interface configured to redirect light between a connector connected to a printed optical board (POB) via an optical waveguide, and a photonic integrated circuit (PIC), the interface involving two-dimensionally distributed waveplates (TDWs) having multiple layers of p-doped and n-doped silicon, the TDWs configured to be driven to change a dielectric constant at a two dimensional location on the TDWs such that the received light is redirected at the two dimensional location.

Abstract: Example implementations described herein are directed to a system involving one or more photonic integrated circuits having multi-mode waveguides and connected to a printed optical board through the use of multi-mode waveguide connectors described herein. The printed optical board can include an embedded multi-mode waveguide bus to facilitate optical signal to and from the photonic integrated circuits. The system can also include a chiplet such as a photonic integrated circuit with a single mode waveguide configured to connect to an optical fiber cable.

Abstract: A display panel includes: a substrate including a first display area and a second display area including a transmission area; a plurality of first display elements arranged in the first display area; a plurality of second display elements arranged in the second display area, the plurality of second display elements each including a pixel electrode and an emission layer; and a pixel defining layer defining an emission area by an opening exposing a central portion of the pixel electrode of each of the plurality of second display elements. In at least one of the plurality of second display elements, a first center of the emission layer and a second center of the emission area do not coincide with each other in a plan view.

Abstract: A protected anode, an electrochemical device including the same, and a method of preparing the electrochemical device. The protected anode may include: an anode layer; and a protective layer including an oxide represented by Formula 1, on the anode layer: In Formula 1, A is at least one of Ge, Sb, Bi, Se, Sn, or Pb; M is at least one of In, Tl, Sb, Bi, S, Se, Te, or Po; A and M are different from each other; and 0<x<100 and 0<y<100.

Abstract: An integrated circuit chip includes a plurality of function blocks; a mode controller configured to convert an input signal, received from an external device through an input/output pin, into an input pattern and test mode setting data which include a plurality of bits, and to output the test mode setting data and a mode switching enable signal when a secure pattern generated therein is the same as the input pattern; and a mode setting module configured to control the plurality of function blocks to operate in a test mode according to the mode setting data, in response to the test mode switching enable signal.

Abstract: The present disclosure provides a computer-implemented method for generating a characteristic information of a malware, which comprises receiving an EXE file of a computer program which is pre-coded for carrying out an attack of a specific malware, the attack corresponding to one of the pre-categorized attack type; generating a first OP Code data set from a first OP Code of attack type of the malware coded in the computer program, the first OP Code being acquired by disassembling the EXE file; acquiring a second OP Code by disassembling a received malware file; and generating a characteristic information of the received malware file based on the comparison result between the first OP Code data set and the second OP Code, the characteristic information relating to the attack type of the received malware file.

Abstract: The present disclosure provides an IoT device which comprise a user application module; an OS API module; a kernel API module; a file system driver module; a file filter driver module; and a network filter driver module. The user application module generates read/write event when an external file is received. The OS API module calls the kernel API module when the event is generated. The kernel API module transmits the read/write event to the file system driver module. The file system driver module generates the read/write operation command and transmits the command to the file filter driver module. The file filter driver module transmits the read/write operation command to the network filter driver module. The network filter driver module generates a exclusive packet including the read/write operation command and transmits the packet to a packet processing application module of a remote server.

Abstract: A CMOS image sensor includes: a substrate containing a potential well stack including: a first p-well, a first n-well disposed below the first p-well, a second p-well disposed below the first n-well, a second n-well disposed below the second p-well, and a third p-well disposed below the second n-well, wherein a first photodiode is formed at the junction between the first p-well and first n-well, a second photodiode is formed at the junction between the first n-well and second p-well, a third photodiode is formed at the junction between the second p-well and the second n-well, and a fourth photodiode is formed at the junction between the second n-well and the third p-well, and each photodiode is disposed at a different respective depth within the substrate; and a plurality of active pixel sensors for converting light received by the photodiodes into electrical charge.

Abstract: A display apparatus includes: a substrate including a main display area, a component area, and a peripheral area; a plurality of main pixel electrodes in the main display area of the substrate; a plurality of auxiliary pixel electrodes in the component area of the substrate; an auxiliary opposite electrode over the auxiliary pixel electrodes, overlapping the auxiliary pixel electrodes, and including a plurality of openings between the auxiliary pixel electrodes; and a shield layer below the auxiliary pixel electrodes and including a plurality of opening portions that overlap the openings of the auxiliary opposite electrode.

Abstract: A color filter structure includes a material stack disposed on a substrate, a material stack disposed in the substrate, a first trench penetrating the material stack and exposing a first metal pad, a scribe line trench penetrating the material stack and exposing a scribe line metal pad, a first filling material partially filling the first trench and substantially filling up the scribe line trench, a second filling material partially filling the first trench and the first filling material and the second filling material together substantially fill up the first trench, and a color filter material covering an optical uniform surface which the material stack, the first filling material and the second filling material together form.

Abstract: Example implementations described herein are directed to an interface configured to redirect light between a connector connected to a printed optical board (POB) via an optical waveguide, and a photonic integrated circuit (PIC), the interface involving two-dimensionally distributed waveplates (TDWs) having multiple layers of p-doped and n-doped silicon, the TDWs configured to be driven to change a dielectric constant at a two dimensional location on the TDWs such that the received light is redirected at the two dimensional location.

Abstract: A pixel circuit is disclosed. The pixel circuit includes a photodiode (PD), a transmission circuit, a reset circuit, a signal storage circuit and a buffer circuit. The transmission circuit is coupled between the PD and an ordinary floating diffusion (FD) node. The reset circuit is coupled to the ordinary FD node. The signal storage circuit is coupled to the ordinary FD node. The buffer circuit is coupled to the ordinary FD node. The signal storage circuit may store a PD signal on a specific node having a reduced leakage path in comparison with the ordinary FD node during a holding phase of the pixel circuit, wherein the holding phase is a time interval starting from a first time point at which the PD signal is stored on the specific node and ending at a second time point at which the pixel circuit is selected for performing a read-out operation.

Abstract: Example implementations described herein are directed to a system involving one or more photonic integrated circuits having multi-mode waveguides and connected to a printed optical board through the use of multi-mode waveguide connectors described herein. The printed optical board can include an embedded multi-mode waveguide bus to facilitate optical signal to and from the photonic integrated circuits. The system can also include a chiplet such as a photonic integrated circuit with a single mode waveguide configured to connect to an optical fiber cable.

Abstract: A pixel circuit includes a front-end circuit, a signal storage circuit, and an output circuit. All of the front-end circuit, the signal storage circuit and the output circuit are coupled to a common floating diffusion (FD) node. The front-end circuit is arranged to generate pixel signals. The signal storage circuit is arranged to store the pixel signals generated by the front-end circuit, wherein when the pixel circuit is selected for performing a read-out operation, the pixel signals stored in the signal storage circuit are pulled up from original voltage levels to other voltage levels higher than the original voltage levels according to a voltage increment applied to a control voltage of the signal storage circuit. When the pixel circuit is selected for performing the read-out operation, the output circuit generates output signals on an output terminal according to voltage levels of the common FD node, respectively.

Abstract: A display apparatus includes a display panel supported within a case having a rear surface including a circular recessed portion. An annular total reflection mirror and an annular half mirror are disposed in the circular recessed portion with an annular light source provided therebetween. A pattern forming member is disposed on an outer side of the annular half mirror and is configured to be reflected by the annular total reflection mirror. A pattern light source is configured to supply light to the pattern forming member so that the pattern is reflected on the annular total reflection mirror. When the annular light source and the pattern light source are turned on, the pattern of the pattern forming member is reflected between the annular total reflection mirror and the annular half mirror.

Abstract: A display apparatus includes a display panel supported within a case having a rear surface including a circular recessed portion. An annular total reflection mirror and an annular half mirror are disposed in the circular recessed portion with an annular light source provided therebetween. A pattern forming member is disposed on an outer side of the annular half mirror and is configured to be reflected by the annular total reflection mirror. A pattern light source is configured to supply light to the pattern forming member so that the pattern is reflected on the annular total reflection mirror. When the annular light source and the pattern light source are turned on, the pattern of the pattern forming member is reflected between the annular total reflection mirror and the annular half mirror.

Abstract: A method for modeling gas production in a coalbed methane gas (CBM) reservoir including (a) dividing a reservoir in a CBM development area into three-dimensional grids to form the three-dimensional grids having a plurality of cells; (b) forming at least one drilling hole in the development area and obtaining a sample for each depth in the reservoir; (c) modeling the amounts of ash, water, and gas for the plurality of cells in the three-dimensional grids; (d) modeling a pressure change over time in each of the cells in the grid under a premise in which a production well is formed in the grids; and (e) performing a Langmuir experiment for a core sample obtained from step (b).

Abstract: An integrated circuit chip includes a plurality of function blocks; a mode controller configured to convert an input signal, received from an external device through an input/output pin, into an input pattern and test mode setting data which include a plurality of bits, and to output the test mode setting data and a mode switching enable signal when a secure pattern generated therein is the same as the input pattern; and a mode setting module configured to control the plurality of function blocks to operate in a test mode according to the mode setting data, in response to the test mode switching enable signal.

Abstract: A pixel circuit is disclosed. The pixel circuit includes a photodiode (PD), a transmission circuit, a reset circuit, a signal storage circuit and a buffer circuit. The transmission circuit is coupled between the PD and an ordinary floating diffusion (FD) node. The reset circuit is coupled to the ordinary FD node. The signal storage circuit is coupled to the ordinary FD node. The buffer circuit is coupled to the signal storage circuit. The signal storage circuit may store a PD signal on a specific node having a reduced leakage path in comparison with the ordinary FD node during a holding phase of the pixel circuit, wherein the holding phase is a time interval starting from a first time point at which the PD signal is stored on the specific node and ending at a second time point at which the pixel circuit is selected for performing a read-out operation.