Patents by Inventor Kilho Lee

Kilho Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10438998
    Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kilho Lee, Gwanhyeob Koh, Hongsoo Kim, Junhee Lim, Chang-Hoon Jeon
  • Publication number: 20190267046
    Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Kilho LEE, Gwanhyeob KOH, Junhee LIM, Hongsoo KIM, Chang-hoon JEON
  • Patent number: 10373653
    Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kilho Lee, Gwanhyeob Koh, Junhee Lim, Hongsoo Kim, Chang-hoon Jeon
  • Publication number: 20190237671
    Abstract: Provided are: a composite polymer semiconductor having a mesh shape formed by mixing a conjugated polymer and an insulating polymer; and a method for producing same. A composite polymer having a mesh structure is produced by introducing a small quantity of a conjugated polymer to an insulating polymer. The produced composite polymer having a mesh structure increases charge mobility, minimizes visible light absorption through the introduction of the small quantity of the conjugated polymer, and thus can be used as a transparent and flexible organic electronic element.
    Type: Application
    Filed: July 13, 2017
    Publication date: August 1, 2019
    Applicant: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Kwanghee LEE, Kilho YU, Byoung Wook PARK
  • Patent number: 10283698
    Abstract: A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 7, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Pil Ko, Kiseok Suh, Kilho Lee, Daeeun Jeong
  • Publication number: 20190088656
    Abstract: Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a peripheral circuit region, forming a data storage layer on the cell region and the peripheral circuit region of the substrate, selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region, forming a top electrode layer on the data storage layer and the mask layer, patterning the top electrode layer to form a plurality of top electrodes on the cell region, and patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region. While patterning the top electrode layer, the mask layer on the peripheral circuit region may serve as an etch stop layer.
    Type: Application
    Filed: April 23, 2018
    Publication date: March 21, 2019
    Inventors: Hong Hyun KIM, Seung Pil KO, Hyunchul SHIN, Kilho LEE
  • Patent number: 10164170
    Abstract: A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kiseok Suh, Byoungjae Bae, Gwanhyeob Koh, Yoonjong Song, Kilho Lee
  • Publication number: 20180358070
    Abstract: Disclosed are a magnetic memory device and a method of fabricating the same. The magnetic memory device comprises a bottom electrode on a substrate, a magnetic tunnel junction pattern including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer that are sequentially stacked on the bottom electrode, and a top electrode on the magnetic tunnel junction pattern. The bottom electrode comprises a first bottom electrode and a second bottom electrode on the first bottom electrode. Each of the first and second bottom electrodes comprises metal nitride. The first bottom electrode has a crystallinity higher than that of the second bottom electrode.
    Type: Application
    Filed: April 27, 2018
    Publication date: December 13, 2018
    Inventors: YOONJONG SONG, KILHO LEE, DAEEUN JEONG
  • Publication number: 20180358056
    Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.
    Type: Application
    Filed: December 26, 2017
    Publication date: December 13, 2018
    Inventors: Kilho LEE, Gwanhyeob KOH, Junhee LIM, Hongsoo KIM, Chang-hoon JEON
  • Publication number: 20180358408
    Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.
    Type: Application
    Filed: December 1, 2017
    Publication date: December 13, 2018
    Inventors: Kilho LEE, Gwanhyeob Koh, Hongsoo Kim, Junhee Lim, Chang-Hoon Jeon
  • Publication number: 20180358555
    Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.
    Type: Application
    Filed: June 16, 2018
    Publication date: December 13, 2018
    Inventors: KILHO LEE, GWANHYEOB KOH, ILMOK PARK, Junhee LIM
  • Publication number: 20180198059
    Abstract: A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.
    Type: Application
    Filed: August 2, 2017
    Publication date: July 12, 2018
    Inventors: Seung Pil KO, Kiseok SUH, Kilho LEE, Daeeun JEONG
  • Publication number: 20180159023
    Abstract: A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.
    Type: Application
    Filed: June 13, 2017
    Publication date: June 7, 2018
    Inventors: Kiseok SUH, BYOUNGJAE BAE, GWANHYEOB KOH, YOONJONG SONG, KILHO LEE
  • Patent number: 9865800
    Abstract: Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shinhee Han, Kilho Lee, Yoonjong Song
  • Publication number: 20170324025
    Abstract: A data storage device and a method for manufacturing the data storage device provide a data storage device having a superior reliability and easy fabrication. The data storage device comprises a substrate including cell and peripheral circuit regions, a first conductive line on the peripheral circuit region, a peripheral contact plug between the substrate and the first conductive line, the peripheral contact plug being in contact with the first conductive line, a second conductive line on the cell region, a plurality of data storage structures between the substrate and the second conductive line, and a wiring structure between the substrate and each of the data storage structures and between the substrate and the peripheral contact plug. The first conductive line includes a bottom surface having a position from the substrate that is lower than a position of a bottom surface of the second conductive line.
    Type: Application
    Filed: February 17, 2017
    Publication date: November 9, 2017
    Inventors: KILHO LEE, Kiseok SUH, Yoonsung HAN, GWANHYEOB KOH, YOONJONG SONG
  • Patent number: 9691816
    Abstract: Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: June 27, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shinhee Han, Kilho Lee, Yoonjong Song
  • Publication number: 20170125666
    Abstract: Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure.
    Type: Application
    Filed: January 12, 2017
    Publication date: May 4, 2017
    Inventors: Shinhee Han, Kilho Lee, Yoonjong Song
  • Patent number: 9595561
    Abstract: A semiconductor memory device includes a cell gate dielectric layer and a cell gate electrode disposed in a gate recess region crossing a cell active portion of a substrate, first and second doped regions disposed in the cell active portion at both sides of the gate recess region, respectively, at least one interlayer insulating layer covering the substrate, a data storage element electrically connected to the second doped region through a contact plug penetrating the at least one interlayer insulating layer, a mold layer covering the data storage element, and a bit line disposed in a cell groove formed in the mold layer. The bit line is in direct contact with a top surface of the data storage element.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: March 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kilho Lee
  • Patent number: 9576846
    Abstract: Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kilho Lee
  • Patent number: 9502291
    Abstract: A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: November 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kilho Lee, Shinhee Han