Patents by Inventor Kilhyun Bang

Kilhyun Bang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113194
    Abstract: Materials and techniques for recessing heterogenous materials in integrated circuit (IC) dies. A first etch may reveal a surface at a desired depth, and a second etch may remove material laterally to reveal sidewalls down to the desired depth of the recess. The first etch may be a cyclical etch, and the second etch may be a continuous etch. The first and second etches may occur in a same chamber. The first and second etches may each be selective to materials with similarities. An IC die may have different, substantially coplanar materials at a recessed surface between and below sidewalls of another material. The recess may have squared profile. The recess may be over transistor structures.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Mekha George, Seda Cekli, Kilhyun Bang, Krishna Ganesan
  • Patent number: 11652045
    Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Mohit K. Haran, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu, Kilhyun Bang, Jason W. Klaus, Reken Patel, Charles Henry Wallace, James Jeong, Ruth Amy Brain
  • Publication number: 20220051975
    Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Applicant: Intel Corporation
    Inventors: Mohit K. Haran, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu, Kilhyun Bang, Jason W. Klaus, Reken Patel, Charles Henry Wallace, James Jeong, Ruth Amy Brain
  • Patent number: 11211324
    Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Mohit K. Haran, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu, Kilhyun Bang, Jason W. Klaus, Reken Patel, Charles Henry Wallace, James Jeong, Ruth Amy Brain
  • Publication number: 20210082805
    Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Mohit K. Haran, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu, Kilhyun Bang, Jason W. Klaus, Reken Patel, Charles Henry Wallace, James Jeong, Ruth Amy Brain