Patents by Inventor Kim Hong Chen
Kim Hong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961779Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.Type: GrantFiled: May 27, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC).Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Patent number: 11133237Abstract: An integrated circuit package and a method of fabrication of the same are provided. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.Type: GrantFiled: April 20, 2020Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Publication number: 20210287956Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.Type: ApplicationFiled: May 27, 2021Publication date: September 16, 2021Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Patent number: 11037852Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.Type: GrantFiled: September 30, 2019Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Publication number: 20200251398Abstract: An integrated circuit package and a method of fabrication of the same are provided. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.Type: ApplicationFiled: April 20, 2020Publication date: August 6, 2020Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Patent number: 10629510Abstract: An integrated circuit package and a method of fabrication of the same are provided. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.Type: GrantFiled: May 21, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Publication number: 20200027809Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Patent number: 10461009Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.Type: GrantFiled: November 30, 2018Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Patent number: 10446520Abstract: Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.Type: GrantFiled: October 2, 2017Date of Patent: October 15, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu Jeng, Shang-Yun Hou, Kim Hong Chen, Wensen Hung, Szu-Po Huang
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Patent number: 10332823Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a substrate including a semiconductor device mounting region, a cover coupled to a perimeter of the substrate, and members disposed between the substrate and the cover. The package includes partitions, with each partition being disposed between two adjacent members. The package includes a fluid inlet port coupled to the cover, and a fluid outlet port coupled to one of the partitions.Type: GrantFiled: December 17, 2018Date of Patent: June 25, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kim Hong Chen, Szu-Po Huang, Shin-Puu Jeng, Wensen Hung
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Publication number: 20190122959Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a substrate including a semiconductor device mounting region, a cover coupled to a perimeter of the substrate, and members disposed between the substrate and the cover. The package includes partitions, with each partition being disposed between two adjacent members. The package includes a fluid inlet port coupled to the cover, and a fluid outlet port coupled to one of the partitions.Type: ApplicationFiled: December 17, 2018Publication date: April 25, 2019Inventors: Kim Hong Chen, Szu-Po Huang, Shin-Puu Jeng, Wensen Hung
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Publication number: 20190096781Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.Type: ApplicationFiled: November 30, 2018Publication date: March 28, 2019Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Patent number: 10157818Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a substrate including a semiconductor device mounting region, a cover coupled to a perimeter of the substrate, and members disposed between the substrate and the cover. The package includes partitions, with each partition being disposed between two adjacent members. The package includes a fluid inlet port coupled to the cover, and a fluid outlet port coupled to one of the partitions.Type: GrantFiled: December 28, 2015Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kim Hong Chen, Szu-Po Huang, Shin-Puu Jeng, Wensen Hung
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Patent number: 10157813Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.Type: GrantFiled: August 14, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Publication number: 20180269127Abstract: An integrated circuit package and a method of fabrication of the same are provided. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.Type: ApplicationFiled: May 21, 2018Publication date: September 20, 2018Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Patent number: 10062665Abstract: An embodiment package includes a first die stack on a surface of a package component, a second die stack on the surface of the package component, and a contour lid over the first die stack and second die stack. The contour lid includes a first thermal conductive portion over the first die stack, a second thermal conductive portion over the second die stack, and a thermal barrier portion between the first thermal conductive portion and the second thermal conductive portion. The thermal barrier portion includes a low thermal conductivity material.Type: GrantFiled: February 22, 2017Date of Patent: August 28, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kim Hong Chen, Wensen Hung, Szu-Po Huang, Shin-Puu Jeng
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Patent number: 9985001Abstract: A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding material, and a redistribution line over the first molding material. The redistribution line is electrically connected to the TV. A second device die is over and bonded to the first device die through flip-chip bonding. A second molding material molds the second device die therein.Type: GrantFiled: November 14, 2016Date of Patent: May 29, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kim Hong Chen, Szu-Po Huang, Shin-Puu Jeng, Wensen Hung
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Patent number: 9978660Abstract: An integrated circuit package and a method of fabrication of the same are introduced. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.Type: GrantFiled: March 14, 2014Date of Patent: May 22, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Patent number: 9941251Abstract: A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion extending laterally beyond a respective edge of the first die. The package further includes a first Thermal Interface Material (TIM) over and contacting a top surface of the first die, a heat dissipating lid having a first bottom surface contacting the first TIM, a second TIM over and contacting the second portion of the second die, and a heat dissipating ring having a portion over and contacting the second TIM. The heat dissipating lid and the heat dissipating ring are discrete components, and at least one of the heat dissipating lid or the heat dissipating ring has a plurality of fins and a plurality of recesses separating the plurality of fins from each other.Type: GrantFiled: February 6, 2017Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Szu-Po Huang, Kim Hong Chen, Shin-Puu Jeng
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Publication number: 20180026008Abstract: Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.Type: ApplicationFiled: October 2, 2017Publication date: January 25, 2018Inventors: Shin-Puu Jeng, Shang-Yun Hou, Kim Hong Chen, Wensen Hung, Szu-Po Huang