Abstract: A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: A manufacturing method of a semiconductor device with a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: A die, comprising a substrate and one or more pillar structures formed over the substrate in a pattern and the method of forming the die.

Abstract: As the functionality, speed and portability of consumer electronics increases, so does the need for more circuitry to be packed into smaller spaces. All this leads to the fact that the size of a device is now becoming more often a function of the circuit board or module size than anything else. In order to achieve size reduction of multi-featured products, passive components on the surface of the circuit need to be eliminated by burying them within the inner layers of the printed wiring board. Embedded passives are passive components placed between the interconnecting substrates of a printed wiring board. Implementation of embedded passives reduces space requirements and enables more silicon devices to be placed on the same sized substrate, thereby allowing functional potential of small electronic devices to increase. However, additional steps are conventionally required for embedding passive components within the interconnect layer between substrates.

Abstract: A semiconductor chip packaging structure is described. The structure comprising of a semiconductor chip interconnected to a recessed lead frame and the resultant assembly encapsulated in a molding compound. The final product is a reverse mounted semiconductor chip in a leadless quad flat pack configuration. A second embodiment allows for the semiconductor chip backside to be exposed for thermal enhancements. Manufacturing methods are also described for the two embodiments disclosed.

Abstract: A predetermined amount of solder (315) is deposited on the free ends of copper posts (310) extending from die pads of a semiconductor die (305). The solder (315) is coated with flux (320) and the semiconductor die (305) is placed on a leadframe (100) with the solder deposits (315) abutting interconnect locations (335) on inner lead portions (101). When reflowed, the solder deposits (315) melt and with the assistance of the flux (320) forms solder interconnects between the free ends of the copper posts (310) and the interconnect locations (335). Due to the predetermined amount of solder (315) deposited on the free ends of the copper posts (310), the molten solder (315) tends not to flow away from the interconnect location (335). Thus, advantageously allowing a substantial portion of the solder deposit (315) to remain at the interconnect locations (335) to form solder interconnects.

Abstract: A predetermined amount of solder (315) is deposited on the free ends of copper posts (310) extending from die pads of a semiconductor die (305). The solder (315) is coated with flux (320) and the semiconductor die (305) is placed on a leadframe (100) with the solder deposits (315) abutting interconnect locations (335) on inner lead portions (101). When reflowed, the solder deposits (315) melt and with the assistance of the flux (320) forms solder interconnects between the free ends of the copper posts (310) and the interconnect locations (335). Due to the predetermined amount of solder (315) deposited on the free ends of the copper posts (310), the molten solder (315) tends not to flow away from the interconnect location (335). Thus, advantageously allowing a substantial portion of the solder deposit (315) to remain at the interconnect locations (335) to form solder interconnects.

Abstract: A mold has at least one vent hole formed in the mold. The vent hole is positioned to allow egress of air from the mold. The vent hole has an inside end and an outside end. The vent hole has a cross section that increases in area from the inside end to the outside end. The vent hole may have a shape of a trapezoidal prism, a truncated pyramid or a truncated cone; the cross section of the vent hole may be a rectangle. A preferred mold has three air vent holes at three corners of the mold. An integrated circuit is placed within the mold. A material to be molded is injected into the mold to encapsulate the integrated circuit. Mold cleaning is facilitated by the shape of the vent, and plastic flashes may be easily removed through the vent hole.

Abstract: An apparatus cuts a substrate having first and second portions, each portion having a respectively different level. A first support surface is located at a first level. The first portion of the substrate is supported by the first support surface. A second support surface is located at a second level different from the first level. The second portion of the substrate is supported by the second support surface. The first and second support surfaces are first and second die surfaces, respectively. A punch cuts the substrate between the first support surface and the second support surface. The punch has a V-shaped cross section. A stripper plate has first and second portions. The punch is positioned between the first and second portions of the stripper plate. The first portion of the substrate is clamped between the first portion of the stripper plate and the first die surface. The second portion of the substrate is clamped between the second portion of the stripper plate and the second die surface.