Patents by Inventor Kimberly Keeton

Kimberly Keeton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10997064
    Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 4, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sanketh Nalli, Haris Volos, Kimberly Keeton
  • Patent number: 10942824
    Abstract: Exemplary embodiments herein describe programming models and frameworks for providing parallel and resilient tasks. Tasks are created in accordance with predetermined structures. Defined tasks are stored as data objects in a shared pool of memory that is made up of disaggregated memory communicatively coupled via a high performance interconnect that supports atomic operations as descried herein. Heterogeneous compute nodes are configured to execute tasks stored in the shared memory. When compute nodes fail, they do not impact the shared memory, the tasks or other data stored in the shared memory, or the other non-failing compute nodes. The non-failing compute nodes can take on the responsibility of executing tasks owned by other compute nodes, including tasks of a compute node that fails, without needing a centralized manager or schedule to re-assign those tasks. Task processing can therefore be performed in parallel and without impact from node failures.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: March 9, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Haris Volos, Kimberly Keeton, Sharad Singhal, Yupu Zhang
  • Publication number: 20210034281
    Abstract: Systems and methods for concurrent reading and writing in shared, persistent byte-addressable non-volatile memory is described herein. One method includes in response to initiating a write sequence to one or more memory elements, checking an identifier memory element to determine whether a write sequence is in progress. In addition, the method includes updating an ingress counter. The method also includes adding process identification associated with a writer node to the identifier memory element. Next, a write operation is performed. After the write operation, an egress counter is incremented and the identifier memory element is reset to an expected value.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Inventors: Milind M. Chabbi, Yupu Zhang, Haris Volos, Kimberly Keeton
  • Patent number: 10854331
    Abstract: A transformation on raw data is applied to produce transformed data, where the transformation includes at least one selected from among a summary of the raw data or a transform of the raw data between different domains. In response to a query to access data, the query is processed using the transformed data.
    Type: Grant
    Filed: October 26, 2014
    Date of Patent: December 1, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Henggang Cui, Kimberly Keeton, Indrajit Roy, Krishnamurthy Viswanathan, Haris Volos
  • Patent number: 10698878
    Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 30, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Stanko Novakovic, Kimberly Keeton, Paolo Faraboschi, Robert Schreiber
  • Publication number: 20200110676
    Abstract: Exemplary embodiments herein describe programming models and frameworks for providing parallel and resilient tasks. Tasks are created in accordance with predetermined structures. Defined tasks are stored as data objects in a shared pool of memory that is made up of disaggregated memory communicatively coupled via a high performance interconnect that supports atomic operations as descried herein. Heterogeneous compute nodes are configured to execute tasks stored in the shared memory. When compute nodes fail, they do not impact the shared memory, the tasks or other data stored in the shared memory, or the other non-failing compute nodes. The non-failing compute nodes can take on the responsibility of executing tasks owned by other compute nodes, including tasks of a compute node that fails, without needing a centralized manager or schedule to re-assign those tasks. Task processing can therefore be performed in parallel and without impact from node failures.
    Type: Application
    Filed: October 8, 2018
    Publication date: April 9, 2020
    Inventors: Haris Volos, Kimberly Keeton, Sharad Singhal, Yupu Zhang
  • Patent number: 10489310
    Abstract: Determining cache value currency using persistent markers is disclosed herein. In one example, a cache entry is retrieved from a local cache memory device. The cache entry includes a key, a value to be used by the computing device, and a marker flag to determine whether the cache entry is current. The local cache memory device also includes a marker location that indicates a location of a marker in a shared persistent fabric-attached memory (FAM). Using a marker location, the marker is retrieved from the shared persistent FAM. From the marker and the marker flag, it is determined whether the cache entry is current. The shared FAM pool is connected to the local cache memory devices of multiple computing devices.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: November 26, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Kimberly Keeton, Yupu Zhang, Haris Volos, Ram Swaminathan, Evan R. Kirshenbaum
  • Publication number: 20190317891
    Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 17, 2019
    Inventors: Sanketh Nalli, Haris Volos, Kimberly Keeton
  • Patent number: 10417215
    Abstract: A system includes processing nodes and shared memory. Each processing node includes a processor and local memory. The local memory of each processing node stores at least a partial copy of the immutable data stage of a dataset. The shared memory is accessible by each processing node and stores a sole copy of the mutable data stage of the dataset and a master copy of the immutable data stage of a dataset.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 17, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Huanchen Zhang, Kimberly Keeton
  • Patent number: 10372602
    Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 6, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Sanketh Nalli, Haris Volos, Kimberly Keeton
  • Publication number: 20190121750
    Abstract: Determining cache value currency using persistent markers is disclosed herein. In one example, a cache entry is retrieved from a local cache memory device. The cache entry includes a key, a value to be used by the computing device, and a marker flag to determine whether the cache entry is current. The local cache memory device also includes a marker location that indicates a location of a marker in a shared persistent fabric-attached memory (FAM). Using a marker location, the marker is retrieved from the shared persistent FAM. From the marker and the marker flag, it is determined whether the cache entry is current. The shared FAM pool is connected to the local cache memory devices of multiple computing devices.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 25, 2019
    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Kimberly Keeton, Yupu Zhang, Haris Volos, Ram Swaminathan, Evan R. Kirshenbaum
  • Publication number: 20190102416
    Abstract: A system includes processing nodes and shared memory. Each processing node includes a processor and local memory. The local memory of each processing node stores at least a partial copy of the immutable data stage of a dataset. The shared memory is accessible by each processing node and stores a sole copy of the mutable data stage of the dataset and a master copy of the immutable data stage of a dataset.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Huanchen Zhang, Kimberly Keeton
  • Publication number: 20180322158
    Abstract: Example implementations relate to changing concurrency control modes. An example implementation includes controlling a concurrency control mode of a data slot that stores a data value. A concurrency control mode of a data slot may be changed from an optimistic concurrency control mode to a multi-version concurrency control mode responsive to detecting a read-write conflict for the data slot. A concurrency control mode of a data slot may be changed from a multi-version concurrency control mode to an optimistic concurrency control mode responsive to detecting that the data slot satisfies a low contention criterion.
    Type: Application
    Filed: May 2, 2017
    Publication date: November 8, 2018
    Inventors: Huanchen Zhang, Kimberly Keeton
  • Publication number: 20180025043
    Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.
    Type: Application
    Filed: March 6, 2015
    Publication date: January 25, 2018
    Inventors: Stanko Novakovic, Kimberly Keeton, Paolo Faraboschi, Robert Schreiber
  • Publication number: 20180018258
    Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.
    Type: Application
    Filed: January 30, 2015
    Publication date: January 18, 2018
    Inventors: Sanketh Nalli, Haris Volos, Kimberly Keeton
  • Publication number: 20170322987
    Abstract: A transformation on raw data is applied to produce transformed data, where the transformation includes at least one selected from among a summary of the raw data or a transform of the raw data between different domains. In response to a query to access data, the query is processed using the transformed data.
    Type: Application
    Filed: October 26, 2014
    Publication date: November 9, 2017
    Inventors: Henggang Cui, Kimberly Keeton, Indrajit Roy, Krishnamurthy Viswanathan, Haris Volos
  • Publication number: 20160253398
    Abstract: The present disclosure is generally related to replicating metadata. A method includes accessing a first file with a first unique identifier at a source location in a storage device, wherein metadata corresponding to the first file is stored in a first database with the first unique identifier. The method includes replicating the first file to produce a second file at a target location, wherein the second file has a second unique identifier. The method includes replicating the metadata and the first unique identifier to a second database. The method includes mapping the second unique identifier to the first unique identifier in the second database.
    Type: Application
    Filed: December 6, 2013
    Publication date: September 1, 2016
    Inventors: Sivashanmugam Jothivelavan, Kannan Rajkumar, Kannan K. Ramesh, Roy Annmary, Pendyala Jaipal, Hamilton De Freitas Coutinho, Guillherme De Campos Magalhaes, Marcelo Bandeira Condotta, Kimberly Keeton, Charles B. Morrey, III, Michael J. Spitzer
  • Patent number: 9389913
    Abstract: A set of jobs to be scheduled is identified (402) in a system including a processing pipeline having plural processing stages that apply corresponding different processing to a data update to allow the data update to be stored. The set of jobs is based on one or both of the data update and a query that is to access data in the system. The set of jobs is scheduled (404) by assigning resources to perform the set of jobs, where assigning the resources is subject to at least one constraint selected from at least one constraint associated with the data update and at least one constraint associated with the query.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: July 12, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kimberly Keeton, Charles B. Morrey, III, Craig A. Souies, Alistair Veitch
  • Patent number: 9130852
    Abstract: Information relating to monitored communications between user machines and a resource of a particular machine is received. Group information that identifies groups of the users is received. Based on the monitored communications and the group information, a summary of a subset of users that have accessed the resource is generated.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: September 8, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark David Lillibridge, Kimberly Keeton
  • Publication number: 20150205834
    Abstract: Example embodiments relate to providing file metadata queries for file systems using representational state transfer compliant (RESTful) application programming interfaces. In example embodiments, a representational state transfer (REST) request that includes requested attributes and search parameters is received. Then, a metadata source including source attributes that correspond to the requested attributes is identified using the translation configuration. The translation configuration of the metadata source is also used to convert the search parameters to obtain converted parameters that are compatible with the metadata source. At this stage, a metadata query for the metadata source that includes the requested attributes and the converted parameters is created.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 23, 2015
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Kimberly Keeton, Evandro Sombrio, Leandro Morais Nunes, Alistair Veitch