Patents by Inventor Kiminori Ishido

Kiminori Ishido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020064345
    Abstract: An optical waveguide path coupling structure is realized without requiring highly accurate alignment.
    Type: Application
    Filed: November 29, 2001
    Publication date: May 30, 2002
    Inventors: Hideo Kikuchi, Kiminori Ishido
  • Patent number: 5746813
    Abstract: The surface protection material for printed circuit boards disclosed is one in which a compound having a benzimidazole derivative as an effective component is adjusted to pH range from 1 to 5 with a salt-forming acid and which is an aqueous solution whose metal content of such a heavy metal as copper, manganese and zinc is not higher than 50 ppm. A copper or copper alloy circuit section surface is brought into contact with the surface protection material aqueous solution, and by using an ion exchange resin or by electrolysis, ions of the heavy metal dissolved out of the circuit section surface due to the contact thereof with the surface protection material aqueous solution are removed. The concentration of the heavy metal in the surface protection material aqueous solution is held within 50 ppm. A surface protection film is formed only on the element mounting pad without being formed on a gold plating layer on a terminal, and this enhances the contact reliability of circuits.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: May 5, 1998
    Assignee: NEC Corporation
    Inventors: Kiminori Ishido, Masahiro Yamaguchi
  • Patent number: 5658611
    Abstract: The surface protection material for printed circuit boards disclosed is one in which a compound having a benzimidazole derivative as an effective component is adjusted to pH range from 1 to 5 with a salt-forming acid and which is an aqueous solution whose metal content of such a heavy metal as copper, manganese and zinc is not higher than 50 ppm. A copper or copper alloy circuit section surface is brought into contact with the surface protection material aqueous solution, and by using an ion exchange resin or by electrolysis, ions of the heavy metal dissolved out of the circuit section surface due to the contact thereof with the surface protection material aqueous solution are removed. The concentration of the heavy metal in the surface protection material aqueous solution is held within 50 ppm. A surface protection film is formed only on the element mounting pad without being formed on a gold plating layer on a terminal, and this enhances the contact reliability of circuits.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 19, 1997
    Assignee: NEC Corporation
    Inventors: Kiminori Ishido, Masahiro Yamaguchi
  • Patent number: 5464725
    Abstract: After pads 2 for mounting parts are formed at desired positions on an insulating board 1 in a circuit forming process using etching resist 3, the etching resist 3 is left on the pads without peeling it off. A first photosolder resist 4 is then formed between the pads 2, exposed to light, and developing using a solvent able to separate the etching resist 3 as a developing liquid, following which the etching resist 3 is peeled off together with the not yet fully hardened first photosolder resist 4. After formation of the first photosolder resist 4, a second photosolder resist is formed on desired areas excluding the interspaces between the pads 2, exposed to light, and developed. Consequently, when a photosolder resist is formed between pads pitched at narrow intervals on a printed wiring board, attachment of the photosolder resist to the pads due to misalignment between the insulating board and a photo-mask can be avoided.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: November 7, 1995
    Assignee: NEC Corporation
    Inventors: Kiminori Ishido, Masahiro Yamaguchi
  • Patent number: 5458907
    Abstract: A method of manufacturing a printed wiring board includes the following steps. A circuit pattern consisting of one material selected from the group consisting of copper and a copper alloy is selectively formed on an insulating substrate, and a solder resist is then formed on the insulating substrate except for a region in which the circuit pattern is formed. A copper oxide and a copper impurity produced on surfaces of the solder resist and the circuit pattern formed on the insulating substrate are removed. A copper oxide coating is uniformly formed on the surface of the circuit pattern from which the copper oxide and copper impurity are removed. A oxidation-proof coating consisting of an imidazole-based pre-flux is formed by substituting the copper oxide coating on the surface of the circuit pattern with imidazole.
    Type: Grant
    Filed: February 7, 1994
    Date of Patent: October 17, 1995
    Assignee: NEC Corporation
    Inventor: Kiminori Ishido
  • Patent number: 5324535
    Abstract: A printed wiring board is selectively covered with solid solder resist pattern implemented by a first solder resist sub-pattern formed from liquid photo-sensitive solder resist and a second solder resist sub-pattern formed from photo-sensitive fry films, and a first area with pads and a second area with a through-hole or via-hole are respectively covered with the first solder resist sub-pattern and the second solder resist sub-pattern so that any peeling of the first solder resist sub-pattern and any residue of the liquid photo-sensitive solder resist in the through-hole or via-hole never take place.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: June 28, 1994
    Assignee: NEC Corporation
    Inventor: Kiminori Ishido
  • Patent number: 5258094
    Abstract: A multilayered board is formed by applying a photosensitive insulating resin layer on a laminated plate on which via holes and a circuit pattern are formed, followed by the formation of photoviaholes through the photoprinting method, plating and etching. Then, the multilayered board is adhered to another multilayered board prepared in the same manner through a prepreg layer and a conductive paste while applying heat and pressure to give a multilayer printed wiring board. According to this method, electrical connections between the conductive layer of the upper-most layer and the inner conductive layers, between the inner conductive layers, and between the lower-most conductive layer and the inner conductive layers can be achieved through the photoviaholes and the conductive paste. Therefore, it is not necessary to form through-holes for the electrical connection therebetween. The multilayer printed wiring boards can be substantially improved in the number of layers and wiring density thereof.
    Type: Grant
    Filed: September 9, 1992
    Date of Patent: November 2, 1993
    Assignee: NEC Corporation
    Inventors: Seiji Furui, Ryo Maniwa, Kiminori Ishido, Keisuke Okada