Patents by Inventor Kimiyoshi Usami

Kimiyoshi Usami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180197600
    Abstract: This invention relates to a semiconductor device that reduces energy consumed to write data to a nonvolatile storing section. A write control circuit 34 stores the same data as that held in MTJ elements MTJ1 and MTJ2. In a store operation storing the data held in a slave latch 32 into the MTJ elements MTJ1 and MTJ2, the write control circuit 34 compares the data stored therein with the data held in the slave latch 32 to control whether or not to write the data to the MTJ elements MTJ1 and MTJ2. If the internally stored data coincides with the data held in the slave latch 32, the write control circuit 34 performs control not to write the data to the MTJ elements MTJ1 and MTJ2.
    Type: Application
    Filed: June 9, 2016
    Publication date: July 12, 2018
    Inventors: Kimiyoshi USAMI, Masaru KUDO
  • Publication number: 20180158500
    Abstract: The present technique relates to a non-volatile memory circuit ensuring a small size and low power consumption while maintaining stable write. A slave latch is provided in an NVDFF, and magnetoresistive elements are connected to the slave latch. A store operation for writing information stored in the slave latch to the magnetoresistive elements is performed before power interruption, and a restore operation for reading out information stored in the magnetoresistive elements to the slave latch is performed at a time of return. The store operation and the restore operation use different paths between the slave latch and the magnetoresistive element. The present technique is applicable to a non-volatile memory circuit.
    Type: Application
    Filed: May 2, 2016
    Publication date: June 7, 2018
    Inventors: Kimiyoshi USAMI, Masaru KUDO
  • Patent number: 8026537
    Abstract: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: September 27, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naohito Kojima, Fumihiro Minami, Kimiyoshi Usami
  • Patent number: 7956678
    Abstract: A power-off controlling circuit and a power-off controlling method that control power-off of an integrated circuit based on the size of leakage currents. The power-off controlling circuit includes a model circuit section that includes a model circuit made by modeling a basic circuit of an integrated circuit, a voltage comparing circuit section that compares an output voltage charged by a leakage current occurred at the model circuit and a preset reference voltage, a decision circuit section that measures an arrival time until the output voltage reaches the reference voltage from the compared result and decides a size of the leakage current from the measured result, and a power-off controlling circuit section that controls power-off of the integrated circuit on the basis of the decided size of the leakage current.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: June 7, 2011
    Assignee: Shibaura Institute of Technology
    Inventor: Kimiyoshi Usami
  • Publication number: 20100052770
    Abstract: A power-off controlling circuit and a power-off controlling method that control power-off of an integrated circuit based on the size of leakage currents. The power-off controlling circuit includes a model circuit section that includes a model circuit made by modeling a basic circuit of an integrated circuit, a voltage comparing circuit section that compares an output voltage charged by a leakage current occurred at the model circuit and a preset reference voltage, a decision circuit section that measures an arrival time until the output voltage reaches the reference voltage from the compared result and decides a size of the leakage current from the measured result, and a power-off controlling circuit section that controls power-off of the integrated circuit on the basis of the decided size of the leakage current.
    Type: Application
    Filed: February 4, 2009
    Publication date: March 4, 2010
    Inventor: Kimiyoshi Usami
  • Publication number: 20070235766
    Abstract: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.
    Type: Application
    Filed: June 14, 2007
    Publication date: October 11, 2007
    Inventors: Naohito Kojima, Fumihiro Minami, Kimiyoshi Usami
  • Patent number: 7109771
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: September 19, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Patent number: 7088161
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: August 8, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Patent number: 7062725
    Abstract: A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is suppressed within a tolerable level without increasing the electric power consumption.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: June 13, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kitahara, Takashi Ishikawa, Kimiyoshi Usami
  • Patent number: 6861882
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20050035803
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Application
    Filed: September 23, 2004
    Publication date: February 17, 2005
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20050035802
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 17, 2005
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Patent number: 6813750
    Abstract: A logic circuit design equipment and a logic circuit design method include analyzing input states of all of first cells, respectively, analyzing leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively, and substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: November 2, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kimiyoshi Usami, Naoyuki Kawabe, Takeshi Kitahara, Masahiro Kanazawa
  • Publication number: 20040183103
    Abstract: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.
    Type: Application
    Filed: January 20, 2004
    Publication date: September 23, 2004
    Inventors: Naohito Kojima, Fumihiro Minami, Kimiyoshi Usami
  • Patent number: 6750680
    Abstract: There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced. In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: June 15, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidemasa Zama, Masayuki Koizumi, Yukiko Ito, Kimiyoshi Usami, Naoyuki Kawabe, Masahiro Kanazawa, Toshiyuki Furusawa
  • Patent number: 6683336
    Abstract: A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefor in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: January 27, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mutsunori Igarashi, Hiroshi Tanaka, Kimiyoshi Usami, Takashi Ishikawa, Masahiro Kanazawa, Chiharu Mizuno
  • Patent number: 6668363
    Abstract: A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: December 23, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumihiro Minami, Takeshi Kitahara, Kimiyoshi Usami, Seiichi Nishio
  • Publication number: 20030140318
    Abstract: A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is suppressed within a tolerable level without increasing the electric power consumption.
    Type: Application
    Filed: March 3, 2003
    Publication date: July 24, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kitahara, Takashi Ishikawa, Kimiyoshi Usami
  • Patent number: 6586982
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: July 1, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20030102898
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Application
    Filed: January 14, 2003
    Publication date: June 5, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa