Patents by Inventor King L Tai
King L Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6313719Abstract: A bandpass planar filter (110) comprises a signal input and a signal output (116), and one or more resonator elements (112, 114) coupled serially end-to-end between the input and the output across gaps (118) that separate the elements from the input, the output, and from each other. The resonator elements form a serpentine shape such that at least two portions of the serpentine shape are positioned side-by-side parallel to each other separated by a spacing (120). The side-by-side portions effect additional coupling between the resonator elements that forms a notch (transmission zero) (204) in the passband (200) of the filter. The input, output, and resonator elements are etched into one surface (106) of a PC board (102); the other surface (104) of the PC board forms a ground plane of the filter, and the substrate (103) of the PC board forms a dielectric of the filter.Type: GrantFiled: March 9, 2000Date of Patent: November 6, 2001Assignee: Avaya Technology Corp.Inventors: Ron Barnett, Yee Leng Low, Zhengxiang Ma, King L Tai, Hui Wu
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Patent number: 5622305Abstract: A method for bonding one body to another, such as a laser device to a submount, uses a metallic layer composed of a Group VB metal, such as niobium, sandwiched between a non-metallic layer and solder layer formed by an approximate Au-Sn eutectic layer. Advantageously the Group VB layer is formed at a submount temperature of less than approximately 201.degree. C., advantageously less than approximately 125.degree. C., and preferably less than approximately 101.degree. C.--advantageously to a thickness in the approximate range 0.05 .mu.m to 0.2 .mu.m, or even thinner if pinholes do not develop. The non-metallic layer is located on one of the bodies, and the other body has a metallic coating advantageously capped with an Au layer.Type: GrantFiled: May 10, 1995Date of Patent: April 22, 1997Assignee: Lucent Technologies Inc.Inventors: Donald D. Bacon, Cheng-Hsuan Chen, Ho S. Chen, Avishay Katz, King L. Tai
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Patent number: 5608262Abstract: Described is a novel packaging of MCM tiles without wire-bond interconnections and in a total thickness which is reduced relative to conventional MCM packaging. The MCM tile includes a substrate with a plurality of peripheral metallizations and at least one chip flip-chip mounted on the substrate. The PWB is provided with an aperture which is smaller than the size of the silicon substrate but larger than the outside dimensions of the mounted chips. The substrate is positioned on the PWB so that its ends overlap areas of the PWB adjacent the aperture and the chips fit into the aperture. Peripheral metallizations on the substrate are interconnected to metallizations on the PWB by either solder reflow technology or conductive adhesive technology.Type: GrantFiled: February 24, 1995Date of Patent: March 4, 1997Assignee: Lucent Technologies Inc.Inventors: Yinon Degani, Thomas D. Dudderar, Byung J. Han, Alan M. Lyons, King L. Tai
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Patent number: 5564617Abstract: A multichip module is assembled using flip-chip bonding technology, a stencil printable solder paste and standard surface mount equipment for interconnecting signaling input/output contact pads on devices within such a multichip module. The disclosed assembly process makes the heretofore difficult and expensive flip chip bonding technique achievable at low cost. The flip chip bonding technique is simplified by use of a solder paste which includes desirable reflow alignment, fluxing and printability characteristics. These desirable characteristics allow the assembly process to be further economically achieved by permitting the use of standard surface mount equipment in the process. High volume production of standard inexpensive modules are thus possible through this process while also achieving the advantage of high density interconnections afforded through the flip-chip bonding technology.Type: GrantFiled: June 7, 1995Date of Patent: October 15, 1996Assignee: Lucent Technologies Inc.Inventors: Yinon Degani, Thomas D. Dudderar, King L. Tai
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Patent number: 5534465Abstract: In accordance with the invention, a multichip circuit is fabricated by providing an active semiconductor substrate comprising a set of isolated components including active components such as transistors, forming on a surface of the substrate a plurality of paths incorporating components from the substrate for interconnecting a plurality integrated circuit devices, and mounting the ICs on the surface in contact with their respectively appropriate paths. The preferred active substrate is similar in structure to a silicon integrated circuit except that the circuit components are interconnected only by the paths interconnecting the ICs. Advantageously the ICs are surface mounted on the substrate.Type: GrantFiled: January 10, 1995Date of Patent: July 9, 1996Assignee: AT&T Corp.Inventors: Robert C. Frye, King L. Tai
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Patent number: 5481205Abstract: A given testing substrate for fast-testing many integrated-circuit electronic devices, one after the other, has a set of mutually insulated collated wiring areas that can be aligned with solder-bump I/O pads of the electronic devices. At the surface of each of the corrugated areas is located a layer that is an electrically conductive durable oxide, or that is itself durable, electrically conductive, and non-oxidizable. During testing, the solder-bump I/O pads of the electronic device being tested are aligned with and pressed against the corrugated wiring areas of the given substrate. Alternatively, the electronic devices being of the electrically programmable variety, such as EPROMs, programming voltages can be delivered to each of the devices, one after the other, through the corrugated wiring areas of a single substrate.Type: GrantFiled: November 23, 1994Date of Patent: January 2, 1996Assignee: AT&T Corp.Inventors: Robert C. Frye, Maureen Y. Lau, King L. Tai
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Patent number: 5461333Abstract: A multi-chip module is composed of two or more integrated-circuit chips located on a substrate such as a dielectrically coated silicon substrate. The chips are interconnected by means of transmission wiring lines. At least some of the chips contain one or more input buffer circuits, each composed of two branches ("legs"). Each such branch contains, in one embodiment, an n-channel MOS transistor connected in series with a pair of series-connected p-channel MOS transistors--whereby, in each such branch, one of the p-channel MOS transistors is located between (intermediate) the other of the p-channel MOS transistors and the n-channel MOS transistor of that same branch. On the other hand, in each buffer circuit, the intermediate p-channel MOS transistors of both branches are cross-coupled.Type: GrantFiled: February 24, 1994Date of Patent: October 24, 1995Assignee: AT&T IPM Corp.Inventors: Joseph H. Condon, Robert C. Frye, Thaddeus J. Gabara, King L. Tai, Scott C. Knauer, deceased, Carroll H. Knauer, executor
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Patent number: 5234153Abstract: A laser device is bonded to a diamond submount by means of a procedure including (1) codepositing an auxiliary layer, on a layer of barrier metal that has been deposited overlying the submount, followed by (2) depositing a wetting layer on the auxiliary layer, and (3) by depositing a solder layer comprising alternating metallic layers, preferably of gold and tin sufficient to form an overall tin-rich gold-tin eutectic composition. The barrier metal is typically W, Mo, Cr, or Ru. Prior to bonding, a conventional metallization such as Ti-Pt-Au (three layers) is deposited on the laser device's bottom ohmic contact, typically comprising Ge. Then, during bonding, the solder layer is brought into physical contact with the laser device's metallization under enough heat and pressure, followed by cooling, to form a permanent joint between them. The thickness of the solder layer is advantageously less than approximately 5 .mu.m. The wetting layer is preferably the intermetallic compound Ni.sub.3 Sn.sub.Type: GrantFiled: August 28, 1992Date of Patent: August 10, 1993Assignee: AT&T Bell LaboratoriesInventors: Donlad D. Bacon, Avishay Katz, Chien-Hsun Lee, King L. Tai, Yiu-Man Wong
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Patent number: 5234149Abstract: One or more metallized chip terminals of an electronic device, such as an integrated circuit chip or a laser chip, in one embodiment are temporarily bonded to one or more metallized substrate pads of a wiring substrate, as for the purpose of electrically testing the electronic device. The composition of the metallized chip terminals is suitably different from that of the metallized substrate pads. The pads and terminals are aligned and electrically connected together with a solder located between them under pressure and a temperature above the melting point of the solder. The solder is cooled, and electrical tests of the electronic device are performed by means of electrical access from testing circuitry to the chip terminals through the substrate pads.Type: GrantFiled: August 28, 1992Date of Patent: August 10, 1993Assignee: AT&T Bell LaboratoriesInventors: Avishay Katz, Chien-Hsun Lee, King L. Tai
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Patent number: 5197654Abstract: A device such as a laser is bonded to a submount such as diamond by a process in which the submount is successively coated with an adhesion layer such as titanium, a barrier layer such as nickel, and a gold-tin solder-metallization composite layer formed by sequential deposition on the barrier layer a number (preferably greater than seven) of multiple alternating layers of gold and tin, the last layer being gold having a thickness that is equal to approximately one-half or less than the thickness of the (next-to-last) tin layer that it contacts immediately beneath it. The bonding is performed under applied heat that is sufficient to melt the solder-metallization composite layer. Prior to the bonding, (in addition to the submount) the device advantageously is coated with gold and optionally with a similar gold-tin solder-metallization composite layer, at least at locations where it comes in contact with the gold-tin solder-metallization composite layer.Type: GrantFiled: November 15, 1991Date of Patent: March 30, 1993Inventors: Avishay Katz, Chien-Hsun Lee, King L. Tai, Yiu-Man Wong
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Patent number: 5043794Abstract: In accordance with the present invention, an integrated circuit package comprises a thermally conductive plate for receiving an integrated circuit and an open rectangular structure of conductor and insulator for surrounding the sides of the circuit and presenting one or more linear arrays of conductive connectors extending laterally through the rectangular structure. Preferably the rectangular structure also includes transverse contacts. Advantageously the plate includes extensions beyond the rectangular structure for acting as cooling fins on opposing sides of the rectangular structure. The linear arrays and cooling fins are preferably on different pairs of parallel sides.Type: GrantFiled: September 24, 1990Date of Patent: August 27, 1991Assignee: AT&T Bell LaboratoriesInventors: King L. Tai, John Thomson, Jr.
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Patent number: 5000532Abstract: A precisely aligned optical fiber switch assembly. A base member has a vee groove for supporting a fixed optical fiber and a second optical fiber in optical alignment with the fixed fiber. The groove contains sections of different dimensions that receive and align sheathed portions of the fibers and groove sections that receive and align unsheathed portions of the fibers. First aligning means on the base member longitudinally position the fixed and second fibers in the groove. Covering means mate with the base member for covering at least part of the sheathed portions of the fibers. Aligning means position the covering means precisely with respect to the base member.Type: GrantFiled: November 6, 1989Date of Patent: March 19, 1991Assignee: AT&T Bell LaboratoriesInventors: Richard T. Kraetsch, Richard J. Pimpinella, Leonard W. Schaper, King L. Tai
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Patent number: 4995695Abstract: Disclosed is a novel "hermetic" optical assembly. A radiation-transmissive member seals an aperture in the assembly housing. The member comprises two major surfaces and a recess that extends from one surface towards the other, with a "septum" between the bottom of the recess and the other surface. An optical or opto-electronic device typically is mounted on the inside surface of the member, and the end of an optical fiber is maintained outside of the assembly in coupling relationship with the device. In a currently preferred embodiment the recess extends from the outward-facing surface of the member and serves to position the end of the optical fiber with respect to a device mounted in a "well" in the inward-facing surface of the member. In another embodiment, the outward facing surface of the member comprises geometrical features (e.g., recesses) that mate with corresponding features (e.g.Type: GrantFiled: August 17, 1989Date of Patent: February 26, 1991Assignee: AT&T Bell LaboratoriesInventors: Richard J. Pimpinella, John M. Segelken, King L. Tai, Ross J. Thompson
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Patent number: 4946236Abstract: An m-input/n-output (e.g., 2.times.2) optical fiber switch is disclosed which alters the location of the fibers by the application of an external force. Illustratively, the switch uses a housing with a diamond-shaped opening extending therethrough, with pairs of optical fibers positioned in orthogonally located V-grooves. Upon the application of an external force, the fibers are moved into the remaining, vacant V-grooves formed by the diamond-shaped opening. In a preferred embodiment, a (2.times.2) switch is magnetically activated.Type: GrantFiled: May 30, 1989Date of Patent: August 7, 1990Assignee: AT&T Bell LaboratoriesInventors: Mindaugas F. Dautartas, Yinon Degani, Richard T. Kraetsch, Richard J. Pimpinella, King L. Tai
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Patent number: 4896937Abstract: A precisely aligned optical fiber switch assembly. A base member has a vee groove for supporting a fixed optical fiber and a second optical fiber in optical alignment with the fixed fiber. The groove contains sections of different dimensions that receive and align sheathed portions of the fibers and groove sections that receive and align unsheathed portions of the fibers. First aligning means on the base member longitudinally position the fixed and second fibers in the groove. Covering means mate with the base member for covering at least part of the sheathed portions of the fibers. Aligning means position the covering means precisely with respect to the base member.Type: GrantFiled: August 2, 1988Date of Patent: January 30, 1990Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: Richard T. Kraetsch, Richard J. Pimpinella, Leonard W. Schaper, King L. Tai
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Patent number: 4767695Abstract: A new method for lithographically patterning nonplanar substrates is disclosed. In accordance with this method, a nonplanar substrate surface is patterned by initially substantially conformably coating the surface with a resist. Conformality is achieved by depositing the resist either from the vapor phase or from a mist. In addition, the motions of the constituents of the vapor or mist should be sufficiently random so that the angular flux distribution at any point on the nonplanar substrate surface to be coated is substantially identical to that at any other point to be coated.Type: GrantFiled: May 28, 1987Date of Patent: August 30, 1988Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: Edith T. T. Ong, King L. Tai, Yiu-Huen Wong
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Patent number: 4703288Abstract: In wafer-scale-integrated assemblies, microminiature transmission lines are utilized as interconnects on the wafer. The extremely small cross-sectional area of a typical such line results in its total line resistance being relatively large. Such a line exhibits signal reflections and resonances. In practice, it is not feasible to eliminate these effects by conventional load termination techniques. As a result, the frequency at which digital signals can be transmitted over such a line is typically limited to well below its so-called resonance limit. In accordance with a feature of the invention, the structural parameters of each line are selected to meet specified design criteria that ensure optimal high-frequency performance of the line.Type: GrantFiled: April 3, 1985Date of Patent: October 27, 1987Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: Robert C. Frye, King L. Tai
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Patent number: 4670770Abstract: In the interest of enhanced yield in the manufacture of "wafer-scale" integrated circuits an assembly of integrated circuit chips is made by placing chips on a substrate. Chips have beveled edges as produced by crystallographically anisotropic chemical etching, and the substrate has wells, grooves, or openings having sloping walls. Chips are positioned on the substrate by bringing sloping walls and beveled edges in juxtaposition, and circuitry on chips is connected to circuitry on the substrate.Type: GrantFiled: February 17, 1984Date of Patent: June 2, 1987Assignees: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventor: King L. Tai
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Patent number: 4496448Abstract: A method and apparatus for fabricating a device is disclosed, which method involves a new reactive ion etching technique. Both a high etch rate and, for example, a high etch selectivity are simultaneously achieved with the inventive reactive ion etching technique by discharging an electrode of the reactive ion etching apparatus in response to a preselected criterion, e.g., a magnitude of a DC bias at said electrode which equals, or exceeds, a preselected value.Type: GrantFiled: October 13, 1983Date of Patent: January 29, 1985Assignee: AT&T Bell LaboratoriesInventors: King L. Tai, Frederick Vratny
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Patent number: 4454221Abstract: A method for enhancing linewidth control during the patterning of a substrate with a resist is disclosed. Resists used in the invention have chemically separated structures characterized by two types of regions of different chemical composition, which different types of regions are interspersed among each other. Because the resists used in the present invention have chemically separated structures, anisotropic wet development of these resists is achievable with an appropriate bicomponent wet developer. Consequently, after exposure, the image formed in a thin, upper layer of the resist is transferred with vertical walls through the thickness of the resist.Type: GrantFiled: April 8, 1982Date of Patent: June 12, 1984Assignee: AT&T Bell LaboratoriesInventors: Cheng-Hsuan Chen, Edith C. Ong, James C. Phillips, King L. Tai