Patents by Inventor Kingo Kurotani
Kingo Kurotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869957Abstract: A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.Type: GrantFiled: August 10, 2021Date of Patent: January 9, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara, Shigeki Koya
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Patent number: 11508834Abstract: A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.Type: GrantFiled: November 13, 2020Date of Patent: November 22, 2022Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara, Shigeki Koya
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Publication number: 20210367066Abstract: A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.Type: ApplicationFiled: August 10, 2021Publication date: November 25, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA, Shigeki KOYA
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Publication number: 20210066479Abstract: A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA, Shigeki KOYA
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Patent number: 10868155Abstract: A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening.Type: GrantFiled: September 11, 2019Date of Patent: December 15, 2020Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara, Shigeki Koya
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Patent number: 10714602Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.Type: GrantFiled: March 15, 2019Date of Patent: July 14, 2020Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara
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Publication number: 20200006536Abstract: A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening.Type: ApplicationFiled: September 11, 2019Publication date: January 2, 2020Applicant: Murata Manufacturing Co., Ltd.Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA, Shigeki KOYA
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Publication number: 20190214489Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.Type: ApplicationFiled: March 15, 2019Publication date: July 11, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA
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Patent number: 10276701Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.Type: GrantFiled: September 19, 2017Date of Patent: April 30, 2019Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara
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Publication number: 20180006144Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.Type: ApplicationFiled: September 19, 2017Publication date: January 4, 2018Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA
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Patent number: 9831329Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.Type: GrantFiled: August 5, 2016Date of Patent: November 28, 2017Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara
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Patent number: 9825156Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.Type: GrantFiled: November 4, 2015Date of Patent: November 21, 2017Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara
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Publication number: 20160343837Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.Type: ApplicationFiled: August 5, 2016Publication date: November 24, 2016Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA
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Publication number: 20160155830Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.Type: ApplicationFiled: November 4, 2015Publication date: June 2, 2016Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA
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Patent number: 7388256Abstract: In a technique to improve the high-frequency power gain of an LDMOS, the distance from the surface of a passivation film covering electrode pads to the rear surface of a silicon substrate is set into 200 ?m or less, or a trench of 2 ?m or more in thickness, in which an insulating film or a conductor is embedded, is formed between a region where a p type impurity is diffused, when a p+ type source penetrating layer is formed, and the channel region of a third LDMOS, so as to extend from the front surface of a semiconductor layer toward a silicon substrate. This trench restrains the p+ type source penetrating layer from spreading to the channel region, thereby lowering the inductance or the resistance of the source and improving the high-frequency power gain.Type: GrantFiled: June 28, 2006Date of Patent: June 17, 2008Assignee: Renesas Technology Corp.Inventors: Kingo Kurotani, Takeshi Sakamoto, Michio Yano, Kenichi Nagura
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Publication number: 20060237787Abstract: In a technique to improve the high-frequency power gain of an LDMOS, the distance from the surface of a passivation film covering electrode pads to the rear surface of a silicon substrate is set into 200 ?m or less, or a trench of 2 ?m or more in thickness, in which an insulating film or a conductor is embedded, is formed between a region where a p type impurity is diffused, when a p+ type source penetrating layer is formed, and the channel region of a third LDMOS, so as to extend from the front surface of a semiconductor layer toward a silicon substrate. This trench restrains the p+ type source penetrating layer from spreading to the channel region, thereby lowering the inductance or the resistance of the source and improving the high-frequency power gain.Type: ApplicationFiled: June 28, 2006Publication date: October 26, 2006Inventors: Kingo Kurotani, Takeshi Sakamoto, Michio Yano, Kenichi Nagura
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Patent number: 7078765Abstract: In a technique to improve the high-frequency power gain of an LDMOS, the distance from the surface of a passivation film covering electrode pads to the rear surface of a silicon substrate is set into 200 ?m or less, or a trench of 2 ?m or more in thickness, in which an insulating film or a conductor is embedded, is formed between a region where a p type impurity is diffused, when a p+ type source penetrating layer is formed, and the channel region of a third LDMOS, so as to extend from the front surface of a semiconductor layer toward a silicon substrate. This trench restrains the p+ type source penetrating layer from spreading to the channel region, thereby lowering the inductance or the resistance of the source and improving the high-frequency power gain.Type: GrantFiled: March 31, 2004Date of Patent: July 18, 2006Assignee: Renesas Technology Corp.Inventors: Kingo Kurotani, Takeshi Sakamoto, Michio Yano, Kenichi Nagura
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Publication number: 20040188805Abstract: In a technique to improve the high-frequency power gain of an LDMOS, the distance from the surface of a passivation film covering electrode pads to the rear surface of a silicon substrate is set into 200 &mgr;m or less, or a trench of 2 &mgr;m or more in thickness, in which an insulating film or a conductor is embedded, is formed between a region where a p type impurity is diffused, when a p+ type source penetrating layer is formed, and the channel region of a third LDMOS, so as to extend from the front surface of a semiconductor layer toward a silicon substrate. This trench restrains the p+ type source penetrating layer from spreading to the channel region, thereby lowering the inductance or the resistance of the source and improving the high-frequency power gain.Type: ApplicationFiled: March 31, 2004Publication date: September 30, 2004Inventors: Kingo Kurotani, Takeshi Sakamoto, Michio Yano, Kenichi Nagura