Patents by Inventor Kinya Mitsumoto

Kinya Mitsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6625070
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: September 23, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20020075732
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Application
    Filed: December 11, 2001
    Publication date: June 20, 2002
    Applicant: Hitachi, Ltd
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20020074572
    Abstract: The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.
    Type: Application
    Filed: December 5, 2001
    Publication date: June 20, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Masao Shinozaki, Takashi Akioka, Kinya Mitsumoto
  • Publication number: 20020071332
    Abstract: A semiconductor memory device having a DDR mode includes a first comparison logic circuit comparing the lower bits of a specified memory address for reading operation with the lower bits of a specified memory address for the preceding writing operation, a second comparison logic circuit detecting if the other bits than the lower bits of the specified memory address for reading operation respectively match the other bits than the lower bits of the specified memory address for the preceding writing operation, and a third comparison logic circuit detecting that, when matching can be obtained in the comparison result from the second comparison logic circuit, the lower bits of the specified memory address or secondary memory address for the reading operation match the lower bits of the specified memory address or secondary memory address for the preceding writing operation, on the comparison result from the first comparison logic circuit.
    Type: Application
    Filed: December 7, 2001
    Publication date: June 13, 2002
    Inventors: Masahiko Nishiyama, Kinya Mitsumoto, Takeshi Agari
  • Patent number: 5920510
    Abstract: A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: July 6, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Seigou Yukutake, Takashi Akioka, Kinya Mitsumoto, Takahiro Nagano, Hideo Maejima
  • Patent number: 5761150
    Abstract: There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.
    Type: Grant
    Filed: May 21, 1996
    Date of Patent: June 2, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Seigoh Yukutake, Kinya Mitsumoto, Takashi Akioka, Masahiro Iwamura, Noboru Akiyama
  • Patent number: 5734616
    Abstract: A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.
    Type: Grant
    Filed: August 8, 1996
    Date of Patent: March 31, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hideto Kazama, Shuichi Miyaoka, Akihiko Emori, Kinya Mitsumoto, Tomoyuki Someya, Masahiro Iwamura, Noboru Akiyama
  • Patent number: 5654931
    Abstract: A semiconductor integrated circuit device is divided into a plurality of blocks, which are individually equipped with signal generate units such that the signal generate units are distributed in the semiconductor integrated circuit device. The semiconductor integrated circuit device is preferably constructed to generate the pulse signal by the pulse generate units which are provided for the individual blocks, after all initial logic operations on the data and control signals have been taken. Thanks to this construction, an SRAM, for example, can have its write recovery time minimized to 0 so that it can achieve high-speed operations. Moreover, since predecoders are provided for the individual blocks, the wiring line number and area in the chip can be reduced to improve the degree of integration of the semiconductor integrated circuit device. Still moreover, signal delay and skew can be reduced in the chip so that high-speed can be achieved.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: August 5, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Tamba, Masahiro Iwamura, Yutaka Kobayashi, Kinya Mitsumoto, Tatsumi Yamauchi, Shuko Yamauchi, Takashi Akioka
  • Patent number: 5646897
    Abstract: A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: July 8, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Seigou Yukutake, Masahiro Iwamura, Kinya Mitsumoto, Takashi Akioka, Noboru Akiyama
  • Patent number: 5638335
    Abstract: A memory device comprising a memory array having a plurality of bits, including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of the memory array, wherein the number of the memory blocks are prescribed to be an integral multiple of three and the input/output bits of the plurality of memory blocks are even. Thereby, the bit structure of the semiconductor memory, having parity bits and which is capable of changing the input/output bits to a plurality of bit structures, can be changed while maintaining the bit structure of the memory blocks even and without increase in propagation delay time.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: June 10, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Akiyama, Seigoh Yukutake, Sadayuki Ohkuma, Akihiko Emori, Takashi Akioka, Shuichi Miyaoka, Shinji Nakazato, Kinya Mitsumoto
  • Patent number: 5631600
    Abstract: A constant current generating circuit is provided with a first current generating circuit unit which generates a first current having a positive temperature dependency and includes a pair of first and second bipolar transistors, a first current mirror circuit comprised of a plurality of first MOS transistors which regulates a current density ratio of the currents fed to the first and second bipolar transistors to be constant and derives the first current and a first circuit disposed between the first and second bipolar transistors and the first current mirror circuit for limiting dependency of the currents flowing through the first and second bipolar transistors on a voltage of a power source applied to the first current mirror circuit, a second current generating circuit unit is also provided which generates a second current having as negative temperature dependency and which includes a third bipolar transistor and a second resistor through which the second current is derived.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: May 20, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Akioka, Kinya Mitsumoto, Yutaka Kobayashi
  • Patent number: 5392246
    Abstract: An area of a semiconductor chip, on which a memory is disposed, is divided into a plurality of memory blocks and redundant memory blocks, each memory block is divided into a plurality of unit arrays of columns for replacing, each redundant memory block is divided into a plurality of unit arrays of redundant columns, a plurality of memory cells are disposed in each unit array of columns for replacing and each unit array of redundant columns, a memory cell group in each unit array of columns for replacing is connected to a word line and a data line, a redundant memory cell group of each unit array of redundant columns is connected to a redundant word line and a redundant data line, a first data selection circuit for controlling data selection with respect to the unit array of redundant columns is disposed in each memory block, a second data selection circuit for controlling data selecting with respect to the unit array group of redundant columns is disposed in each redundant memory block, and a third data selec
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: February 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Akiyama, Kinya Mitsumoto, Takashi Akioka, Seigoh Yukutake
  • Patent number: 5392250
    Abstract: In a semiconductor memory device of the present invention, data read from a memory cell to a pair of complementary data lines or a pair of common data lines are fed directly to an output circuit not through any sense amplifier. As a result, the delay time of the sense amplifier itself is omitted from the address access time of the conventional semiconductor memory device using the sense amplifier, so that the semi-conductor memory device of the present invention can have its address access time made shorter than that of the conventional semiconductor memory device.
    Type: Grant
    Filed: January 15, 1993
    Date of Patent: February 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Kinya Mitsumoto, Yoshikazu Iida, Hiroki Miyashita, Kazunori Onozawa
  • Patent number: 5367490
    Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.
    Type: Grant
    Filed: October 27, 1992
    Date of Patent: November 22, 1994
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd
    Inventors: Kazuhiro Akimoto, Masami Usami, Katsumi Ogiue, Hiroshi Murayama, Hitoshi Abe, Masamori Kashiyama, Yoshikuni Kobayashi, Satoru Isomura, Kinya Mitsumoto
  • Patent number: 5050127
    Abstract: A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.
    Type: Grant
    Filed: October 19, 1989
    Date of Patent: September 17, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Kinya Mitsumoto, Shinji Nakazato, Yoshiaki Yazawa, Masanori Odaka, Hideaki Uchida, Nobuaki Miyakawa
  • Patent number: 5014242
    Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.
    Type: Grant
    Filed: December 8, 1988
    Date of Patent: May 7, 1991
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Kazuhiro Akimoto, Masami Usami, Katsumi Ogiue, Hiroshi Murayama, Hitoshi Abe, Masamori Kashiyama, Yoshikuni Kobayashi, Satoru Isomura, Kinya Mitsumoto
  • Patent number: 4829479
    Abstract: A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.
    Type: Grant
    Filed: October 15, 1987
    Date of Patent: May 9, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Kinya Mitsumoto, Shinji Nakazato, Yoshiaki Yazawa, Masanori Odaka, Hideaki Uchida, Nobuaki Miyakawa
  • Patent number: 4748487
    Abstract: A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.p) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.
    Type: Grant
    Filed: May 26, 1987
    Date of Patent: May 31, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Uchida, Kinya Mitsumoto, Yoshiaki Yazawa, Shinji Nakazato, Masanori Odaka
  • Patent number: 4682200
    Abstract: A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.P) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.
    Type: Grant
    Filed: April 14, 1986
    Date of Patent: July 21, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Uchida, Kinya Mitsumoto, Yoshiaki Yazawa, Shinji Nakazato, Masanori Odaka
  • Patent number: 4665505
    Abstract: A write circuit for a semiconductor storage device which comprises a data output stage constructed by a composite circuit including at least one MOS transistor logic circuit and bipolar transistor. The Mos transistor circuit operates in response to an input signal to control the on-off states of at least one of the bipolar transistors. The write circuit implements less power consumption.
    Type: Grant
    Filed: December 24, 1984
    Date of Patent: May 12, 1987
    Assignees: Hitachi, Ltd., Hitachi Haramachi Semi-Conductor Ltd.
    Inventors: Nobuaki Miyakawa, Yoshiaki Yazawa, Shoichi Ozeki, Kinya Mitsumoto