Abstract: A memory system includes a non-volatile memory including a plurality of memory cells; and a controller. The controller is configured to perform a multi-step write operation to write multi-bit data with respect to each of target memory cells through a first programming to set a first threshold voltage and then a second programming to set a second threshold voltage. The controller, during the multi-step write operation, determines a time period elapsed from a first time at which the first programming with respect to a first memory cell of the target memory cells has been performed, and varies a second time at which the second programming with respect to the first memory cell is performed based on whether the time period is greater than a first threshold.

Abstract: A memory controller receives first, second, and third data by first, second, and third reads, specifying a first address, and respectively specifying first, second, and third read voltages higher in this order. The controller instructs a memory to execute a fourth read specifying a fourth read voltage lower than the first read voltage and the first address when a first difference between a first-value-bit count of the first data and an expected value is smaller than a second difference between a first-value-bit count of the third data and the expected value. The memory controller instructs the memory to execute a fifth read specifying a fifth read voltage higher than the third read voltage and the first address when the first difference is larger than the second difference.

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

Abstract: A display apparatus includes circuitry to receive an input of hand drafted input data displayed as an object on a display. The circuitry converts the hand drafted input data into one of a text and a shape and determines whether the one of the text and the shape corresponds to a corresponding one of a recognition character string and a recognition shape set in advance. In a case that the one of the text and the shape corresponds to the corresponding one of the recognition character string and the recognition shape, the circuitry displays a display component based on the corresponding one of the recognition character string and the recognition shape. The display component is for receiving a user operation for generating an electronic signature in relation to the object. The circuitry generates the electronic signature in response to receiving selection of the display component.

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m?1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.

Abstract: A network device includes circuitry configured to: generate log information; acquire a status notification from a device that records the log information, the status notification being designated by the device; change a processing mode of the log information, based on the acquired status notification; and transmit, to the device, based on the changed processing mode, the generated log information.

Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m?1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

Abstract: A memory system includes a memory chip and a memory controller. The memory chip has a first plane and a second plane. A threshold voltage corresponding to multiple bit data is set for each of the memory cells. The memory controller causes the memory chip to execute a first read process on the first plane and the second plane in parallel by using a plurality of first read voltages different from each other for the first plane and the second plane. The first read process being a process of reading a data group of one bit among the multiple bits by using the first read voltages. The memory controller subsequently adjusts the voltage levels of the first read voltages on the basis of the data group read from the memory cells of the first plane and the data group read from the memory cells of the second plane.

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

Abstract: A communication control apparatus for controlling communication between at least one communication apparatus and a plurality of network apparatuses residing on a plurality of networks includes a plurality of communication controllers respectively provided for the plurality of networks.

Abstract: A memory system includes a memory chip and a memory controller. The memory chip has a first plane and a second plane. A threshold voltage corresponding to multiple bit data is set for each of the memory cells. The memory controller causes the memory chip to execute a first read process on the first plane and the second plane in parallel by using a plurality of first read voltages different from each other for the first plane and the second plane. The first read process being a process of reading a data group of one bit among the multiple bits by using the first read voltages. The memory controller subsequently adjusts the voltage levels of the first read voltages on the basis of the data group read from the memory cells of the first plane and the data group read from the memory cells of the second plane.

Abstract: A memory system includes a memory unit with a plurality of first memory cells connected to a first word line and a memory controller to control the memory unit to write data in page units equal in size to the number of first memory cells. The memory unit is configured to write a plurality of pages of data to the plurality of first memory cells and then read each page of data thus written. The memory controller determines whether or not each page of data, as read from the plurality of first memory cells, satisfies a predetermined condition, and registers a determination result for each page indicating whether the predetermined condition was satisfied.

Abstract: A network device includes circuitry configured to: generate log information; acquire a status notification from a device that records the log information, the status notification being designated by the device; change a processing mode of the log information, based on the acquired status notification; and transmit, to the device, based on the changed processing mode, the generated log information.

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

Abstract: A communication control apparatus for controlling communication between at least one communication apparatus and a network apparatus residing on one network among a plurality of networks includes multiple communication controllers respectively provided for the plurality of networks. Each communication controller includes a memory that stores operation determination information to be used for determining processing to be performed on transmission-and-reception information, the transmission-and-reception information to be transmitted or received by the communication controller with respect to other communication controller or the network apparatus on the network and circuitry that acquires the operation determination information in response to receiving the transmission-and-reception information, and performs operation corresponding to the acquired operation determination information on the transmission-and-reception information.

Abstract: A communication system includes: a terminal device; and a communication device. The communication device includes: a first communication unit configured to perform communication with the terminal device through first wireless communication based on connection information; a second communication unit configured to perform communication via a network; and a connection control unit configured to permit the terminal device, which performs communication with the first communication unit based on the connection information, to connect to the network via the second communication unit.

Abstract: A memory system includes a memory unit with a plurality of first memory cells connected to a first word line and a memory controller to control the memory unit to write data in page units equal in size to the number of first memory cells. The memory unit is configured to write a plurality of pages of data to the plurality of first memory cells and then read each page of data thus written. The memory controller determines whether or not each page of data, as read from the plurality of first memory cells, satisfies a predetermined condition, and registers a determination result for each page indicating whether the predetermined condition was satisfied.

Abstract: A sealed compressor comprises a sealed container (101) which accommodates an electric component (105) and a compression component (106); wherein the compression component (106) includes a shaft (110) including a main shaft section (111) and an eccentric shaft section (112), a cylinder block (114), a piston (126), and a main bearing unit (120) mounted to the cylinder block (114) and supporting the main shaft section (112) such that the main shaft section (112) is rotatable, a thrust ball bearing (132) mounted to a thrust surface (130) of the main bearing unit (120); and the thrust ball bearing (132) includes a plurality of balls (134) held in a cage (133), an upper race (135) having main surfaces one of which is in contact with upper portions of the balls (134); and a lower race (136) having main surfaces one of which is in contact with lower portions of the balls (134) and; a restricting means for restricting a displacement of the upper race (135) with respect to the shaft (110).