Patents by Inventor Kiyofumi Ochii

Kiyofumi Ochii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5796137
    Abstract: The gate of a selection transistor is connected to a word line and the source thereof is connected to a bit line. The drain of the selection transistor is connected to a storage node constituting a capacitor of thin film transistor structure. The capacitor has a plate electrode insulated from the storage node, that portion of the plate electrode which is disposed in opposition to the storage node is formed to have an impurity concentration lower than the remaining portion thereof and an inverted layer is formed in the corresponding portion according to data stored in the storage node. The plate electrode is connected to pulse generation means, a pulse signal is output from the pulse generation means in the data readout operation and the potential of the plate electrode is raised by the pulse signal.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: August 18, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyofumi Ochii
  • Patent number: 5712652
    Abstract: A liquid crystal display device of low power consumption is disclosed, which is suitable for use with a portable data processing apparatus, in particular.
    Type: Grant
    Filed: February 16, 1996
    Date of Patent: January 27, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Sato, Shuichiro Ishizawa, Nozomu Harada, Kiyofumi Ochii, Shigeyuki Hayakawa, Yoshiro Aoki
  • Patent number: 5661678
    Abstract: A semiconductor memory device comprises a memory cell array including NAND type memory cell units arranged in matrix and having a plurality of dynamic type memory cells connected in series, a plurality of word lines, a plurality of bit lines arranged within the memory cell array, the plurality of bit lines including a bit line pairs which are arranged adjacent to each other or between which at least one bit line is interposed, and a plurality of sense amplifiers of a folded bit line type, provided in each of the plurality of bit line pairs, in which the memory cells are provided in positions corresponding to intersections of the bit lines and the word lines, and complementary data are written to two memory cells connected to each of the plurality of bit line pairs and one word line, and the two memory cells store one-bit data.
    Type: Grant
    Filed: December 12, 1995
    Date of Patent: August 26, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Yoshida, Yukihito Oowaki, Takehiro Hasegawa, Kiyofumi Ochii, Masayuki Koizumi
  • Patent number: 5563434
    Abstract: The gate of a selection transistor is connected to a word line and the source thereof is connected to a bit line. The drain of the selection transistor is connected to a storage node constituting a capacitor of thin film transistor structure. The capacitor has a plate electrode insulated from the storage node, that portion of the plate electrode which is disposed in opposition to the storage node is formed to have an impurity concentration lower than the remaining portion thereof and an inverted layer is formed in the corresponding portion according to data stored in the storage node. The plate electrode is connected to pulse generation means, a pulse signal is output from the pulse generation means in the data readout operation and the potential of the plate electrode is raised by the pulse signal.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: October 8, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyofumi Ochii
  • Patent number: 5557566
    Abstract: A semiconductor nonvolatile RAM having a dynamic RAM cell and an E.sup.2 PROM cell. The dynamic RAM cell includes a first transistor having a current path having one end connected to a bit line and a gate connected to a word line. A storage region is connected to another end of the current path. The E.sup.2 PROM cell includes a second transistor including a source region, a drain region, a channel region having first and second parts between the source and drain regions, a floating gate above the first part of the channel region and the source region, and a control gate. The drain of the second transistor is connected to the another end of the current path of the first transistor. Another end of the storage region is above the second part of the channel region and the floating gate. The channel region of the second transistor is rendered conductive in accordance with data stored in the storage region of the dynamic RAM cell.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: September 17, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyofumi Ochii
  • Patent number: 5517454
    Abstract: A semiconductor memory device including dynamic memory cells for which refresh operation is required, wherein one fundamental cycle consists of a normal operation for carrying out writing or reading into or from the memory cells and a refresh operation. This semiconductor memory device comprising: a refresh signal generating circuit supplied with a clock signal to generate a refresh signal indicating start of refresh; a count signal generating circuit supplied with the clock signal to generate a count signal required for selection of a memory cell to be refreshed, a refresh counter circuit supplied with the refresh signal and the count signal to select a word line and a bit line to which a memory cell to be refreshed is connected; and a precharge circuit supplied with the refresh signal to carry out precharge of the bit line for refresh.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: May 14, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Sato, Kiyofumi Ochii, Yukihiro Urakawa
  • Patent number: 5317532
    Abstract: A semiconductor memory device which comprises memory cells arranged in rows and columns on a semiconductor substrate, each having one transistor and one capacitor, word lines each connected to memory cells in the same row, bit lines each connected to memory cells in the same column, a plate voltage generating circuit for generating a capacitor plate voltage at the time of normal operation, a negative pulse generating circuit responsive to a control signal supplied thereto at the time of voltage stress testing, for generating a pulse voltage of negative polarity, switch circuits for supplying the pulse voltage of negative polarity output from the negative pulse generating circuit, to the plate electrodes of the capacitors of all memory cells simultaneously, in place of the output of the plate voltage generating circuit, and a switch control circuit responsive to a control signal supplied thereto during voltage stress testing, for controlling the switch circuits.
    Type: Grant
    Filed: March 10, 1992
    Date of Patent: May 31, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyofumi Ochii
  • Patent number: 5315546
    Abstract: A MOS transistor has a floating gate, which forms a memory cell of EPROM, and a control gate. The control gate is formed of a thin film. An impurity concentration of a region corresponding to the floating gate is lower than that of the other regions. The region having low impurity concentration functions as a channel region of a thin film transistor. The floating gate functions as a gate of the thin film transistor. In the memory cell in which an electron is written in the floating gate, a threshold voltage of the thin film transistor rises, and the thin film transistor is set to be in an off state. In the memory cell in which no electron is written in the floating gate, the threshold voltage of the thin film transistor lowers, and the thin film transistor is set to be in an on state.
    Type: Grant
    Filed: May 29, 1991
    Date of Patent: May 24, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyofumi Ochii
  • Patent number: 5282162
    Abstract: The gate of a transistor Q1 serving as a selection transistor is connected to a word line and the source thereof is connected to a bit line BL. The gate of a transistor Q2 serving as a cell capacitor is connected to the drain of the transistor Q1 and the drain thereof is connected to a pulse generation circuit. Whether an inverted layer is formed in the channel region of the transistor Q2 or not is determined according to the stored data. An inverted layer is formed in the channel region of the transistor Q2 having data "1" stored as storage data. The source of the transistor Q2 is connected to the gate of a transistor Q3. The drain of the transistor Q3 is connected to a pulse generation circuit 11 and the source thereof is connected to the drain of the transistor Q1. The transistor Q2 having an inverted layer formed therein is turned on when a preset voltage is supplied from the pulse generation circuit 11 in the stored data reading operation, and in this case, the transistor Q3 is turned on.
    Type: Grant
    Filed: May 23, 1991
    Date of Patent: January 25, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyofumi Ochii
  • Patent number: 5281843
    Abstract: First and second N-channel MOS transistors, each serving as a transfer gate, have their current paths connected, at their first ends, to bit lines, respectively, and their gates connected to a word line. Third and fourth N-channel MOS transistors, forming a flip-flop circuit, have their current paths connected, at their first ends, to the second ends of the current paths of the first and second transistors, respectively, and at their second ends, to a first power supply. The first ends of the current paths of the third and fourth transistors are connected to first ends of first and second thin-film transistors, respectively. The second ends of the current paths of the first and second thin-film transistors are connected to a second power supply. Each of the first and second thin-film transistors has first and second gates on both sides of its channel region.
    Type: Grant
    Filed: June 19, 1991
    Date of Patent: January 25, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyofumi Ochii, Shigeyuki Hayakawa
  • Patent number: 5278459
    Abstract: According to this invention, there is provided a semiconductor static data memorizing apparatus including, a first power supply terminal, a second power supply terminal, a first TFT (thin film transistor), the first TFT having a first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a first data storage node for memorizing the second data, a second TFT, the TFT having the first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a second data storage node for memorizing the data, a third TFT, the third TFT having a second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the first data storage node, and a fourth TFT, the fourth TFT having the second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the second data storage node, wherein a gate of the first T
    Type: Grant
    Filed: November 14, 1991
    Date of Patent: January 11, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masataka Matsui, Kiyofumi Ochii, Katsuhiko Sato
  • Patent number: 5276647
    Abstract: SRAM comprises a word line driving circuit selecting a predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or word lines, which are more than the number of word lines to be selected at the time of the normal operation, at the time of a voltage stress applying test, and a bit line load circuit applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines or applying the bias voltage, which is lower than the bias voltage at the time of the normal operation, at the time of the voltage stress test.
    Type: Grant
    Filed: December 26, 1991
    Date of Patent: January 4, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masataka Matsui, Tohru Furuyama, Shigeyuki Hayakawa, Kiyofumi Ochii
  • Patent number: 5262988
    Abstract: A dynamic memory cell includes a first MOS transistor for data transfer connected at one end to a read/write node and having a gate connected to a transfer gate control line, a second MOS transistor having a gate connected to a first storage node on the other end side of the first MOS transistor and a gate capacitor used as a data storage capacitor, a third MOS transistor for refresh current supply connected at one end to the first storage node, and a resistor element or switching element connected between the gate of the third MOS transistor and the other end of the second MOS transistor. The cell itself has the refresh current supplying capability and it is not necessary to effect the refresh operation on the read/write node side by turning on the charge transfer transistor.
    Type: Grant
    Filed: May 14, 1992
    Date of Patent: November 16, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyofumi Ochii
  • Patent number: 5239501
    Abstract: In a static memory, a memory cell is constituted by only the same-channel MOSFETs. With the MOSFETs of the same channel, no well isolation region is required, and a cell size can be decreased. Moreover, the high potential side power source of a flip-flop can be used as a read word line. Thus the read word line can be driven by an ECL logic circuit.
    Type: Grant
    Filed: July 24, 1991
    Date of Patent: August 24, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masataka Matsui, Kiyofumi Ochii
  • Patent number: 5204834
    Abstract: A plurality of static memory cells 10 each comprising a thin film transistor acting as a load are connected to a power source wiring 12 positioned within a memory cell array. The power source wiring 12 positioned within the memory cell array is connected via a resistor circuit 14 to a power source wiring 13 of a low resistivity, which is positioned outside the memory cell array.
    Type: Grant
    Filed: May 24, 1991
    Date of Patent: April 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyofumi Ochii, Shigeyuki Hayakawa
  • Patent number: 5157474
    Abstract: A static memory in which polysilicon thin film transistors serve as load elements in a memory cell, and the gate electrodes of the polysilicon thin film transistors are formed of diffusion regions. In the static memory, high quality uniform TFTS are formed, and the oxidation films of the TFTs can be thin, without using a complex manufacturing technique.
    Type: Grant
    Filed: April 10, 1990
    Date of Patent: October 20, 1992
    Assignee: Kabushiki Kaishi Toshiba
    Inventor: Kiyofumi Ochii
  • Patent number: 5132929
    Abstract: A static random access memory has a plurality of memory cells. Each memory cell is made up of two high-resistance resistors functioning as load elements, and a flip-flop circuit. The flip-flop circuit is made up of two inverters including MOS transistors which are formed in a substrate and used as drive elements. The sources of the two MOS transistors are coupled to each other and electrically isolated from the substrate. Another MOS transistor is connected between the common source of the flip-flop MOS transistors and the source of a power-supply voltage. A MOS transistor is coupled between the common source of the MOS transistors and the source of a ground voltage. A plurality of bit lines supplies data to, and receives data from, the memory cells. A resistance element is connected between each bit line and the source of the power-supply voltage, and an output terminal outputs the voltage at one end of this resistance element. Two different voltages are applied to the sources of the two MOS transistors.
    Type: Grant
    Filed: December 22, 1988
    Date of Patent: July 21, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyofumi Ochii
  • Patent number: 4958316
    Abstract: A static random access memory comprising a semiconductor substrate, a well region formed in the substrate and containing at least one memory cell, and a power-supply terminal connected to the well region, for applying a given bias voltage to the well region.
    Type: Grant
    Filed: December 22, 1988
    Date of Patent: September 18, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyofumi Ochii, Masataka Matsui, Osamu Ozawa
  • Patent number: 4907059
    Abstract: A semiconductor device has a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; an interconnection layer, containing an impurity of a second conductivity type, for connecting the first and second semiconductor regions; and a third semiconductor region of the second conductivity type which is formed in the first semiconductor region upon diffusion of the impurity from the interconnection layer to the first semiconductor region, the first and third semiconductor regions being adapted to form a p-n junction diode.
    Type: Grant
    Filed: February 5, 1988
    Date of Patent: March 6, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyoshi Kobayashi, Kiyofumi Ochii, Tatsuya Inatsuki
  • Patent number: 4903096
    Abstract: There is disclosed a memory cell in which a low resistance polycrystal silicon layer and a high resistance polycrystal silicon layer are connected to each other with a barrier metal layer provided therebetween and formed in a contact hole of an insulation film.
    Type: Grant
    Filed: October 25, 1988
    Date of Patent: February 20, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fujio Masuoka, Kiyofumi Ochii