Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

Abstract: Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times When the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

Abstract: Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.

Abstract: Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.

Abstract: Disclosed herein is an apparatus that includes a first internal-potential generation circuit that generates a first internal potential from a power supply potential and that outputs the first internal potential to a first node, and an internal-potential force circuit that includes a first switch element provided between the first node and a second external terminal. The internal-potential force circuit causes the first switch element to enter into an off-state when the test signal supplied to a third external terminal is activated and a potential level of a first external terminal is a first level, and causes the first switch element to enter into an on-state when the test signal supplied to the third external terminal is activated and the potential level of the first external terminal is a second level different from the first level.

Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).

Abstract: Disclosed here is an apparatus that comprises a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.

Abstract: Disclosed herein is a semiconductor device that includes: an internal voltage generator configured to produce an internal voltage in a first mode and stop producing the internal voltage in a second mode; a level shifter configured to receive the internal voltage, a first voltage and a first signal, in order to convert the first signal from a voltage level of internal voltage to a voltage level of the first voltage and output the first signal with the voltage level of the first voltage; and a logic circuit configured to produce the first signal, the logic circuit being supplied with the internal voltage in the first mode and supplied with the first voltage in the second mode.

Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.

Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).

Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.

Abstract: Disclosed herein is an apparatus that includes a first internal-potential generation circuit that generates a first internal potential from a power supply potential and that outputs the first internal potential to a first node, and an internal-potential force circuit that includes a first switch element provided between the first node and a second external terminal. The internal-potential force circuit causes the first switch element to enter into an off-state when the test signal supplied to a third external terminal is activated and a potential level of a first external terminal is a first level, and causes the first switch element to enter into an on-state when the test signal supplied to the third external terminal is activated and the potential level of the first external terminal is a second level different from the first level.

Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized.

Abstract: A device may include, but is not limited to, a bit line; a power line supplied with a power voltage; a sense amplifier circuit amplifying a voltage of the bit line by using the power voltage of the power line; and a control circuit configured to respond to an active command and supply, as the power voltage, the power line with a first voltage during a first period and a second voltage lower than the first voltage during a second period. The control circuit is further configured to respond to a refresh command and supply, as the power voltage, the power line with the second voltage during both the first and second periods.

Abstract: A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal voltage to increase with the rise of the power supply voltage.

Abstract: Disclosed herein is a semiconductor device that includes: an internal voltage generator configured to produce an internal voltage in a first mode and stop producing the internal voltage in a second mode; a level shifter configured to receive the internal voltage, a first voltage and a first signal, in order to convert the first signal from a voltage level of internal voltage to a voltage level of the first voltage and output the first signal with the voltage level of the first voltage; and a logic circuit configured to produce the first signal, the logic circuit being supplied with the internal voltage in the first mode and supplied with the first voltage in the second mode.

Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized.