Patents by Inventor Kiyokazu Okada

Kiyokazu Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220290402
    Abstract: There is provided a work machine enabling an operator who operates the work machine to remotely control another work machine with a feeling that the work machine is operated. An work machine 100 includes an operation mechanism 52 provided in a ride section 50 and to be operated by the operator, an actuator 63 (a driving mechanism) configured to drive the work machine 100, communication equipment 53, and a master control device 61. The master control device 61 controls an operation of the actuator 63 depending on an operation mode of the operation mechanism 52 by the operator and causes the communication equipment 53 to transmit an operation command signal to the other work machine 200 after generating the operation command signal.
    Type: Application
    Filed: April 13, 2020
    Publication date: September 15, 2022
    Inventors: Tomofumi OKADA, Kiyokazu TANAKA
  • Publication number: 20220275602
    Abstract: A work machine is provided that is capable of causing an action object of the work machine to act in a manner intended by an operator. A work machine includes a traveling body 11 (base body), a grasping mechanism 14 (working unit) which is displaceable with respect to the traveling body 11 and performs a processing action on a vehicle OB (work target object), an operation accepting unit 23a, a controller 23 which controls displacement and the processing action of the grasping mechanism 14 in accordance with an operation accepted by the operation accepting unit 23a and an operation amount of the operation, and a distance acquisition unit 23f which acquires a distance between the grasping mechanism 14 and one region defined based on a position of the vehicle OB. The controller 23 adjusts a displacement amount or an action amount of the processing action of the grasping mechanism 14 with respect to the operation amount in accordance with the distance.
    Type: Application
    Filed: April 13, 2020
    Publication date: September 1, 2022
    Inventors: Tomofumi OKADA, Kiyokazu TANAKA
  • Patent number: 8914226
    Abstract: Devices, methods, and programs access map information including link information related to links that constitute a road, acquire a current location of a vehicle at unit time intervals, and acquire traffic information, which includes a distributed traffic congestion level of each link at predetermined time intervals. Each time the vehicle exits a link, the devices, methods, and programs sequentially store the exited link in an exited link train based on the map information. If the traffic information has been received, the devices, methods, and program store the distributed traffic congestion level included in the received traffic information as a traffic congestion level in association with a portion of the exited link train within a range from the current location at a received time point when the traffic information has been received to a location that is a predetermined distance behind the current location at the received time point.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: December 16, 2014
    Assignee: Aisin AW Co., Ltd.
    Inventors: Takayuki Miyajima, Satoshi Hirano, Kiyokazu Okada
  • Patent number: 8781717
    Abstract: Devices, methods, and programs determine whether a vehicle has exited a link based on map information. If so, the devices, methods, and programs acquire a travel traffic congestion level of the exited link based on travel information within the exited link, and determine whether the travel traffic congestion level of the exited link coincides with a distributed traffic congestion level at a time when the vehicle exited. If not, the devices, methods, and programs determine whether the traffic information has been updated and the distributed traffic congestion level has been changed within the exited link, and if so, acquire a distribution time rate of each distributed traffic congestion level within the exited link. The devices, methods, and programs determine a traffic congestion level of the exited link based on the distribution time rate of each acquired distributed traffic congestion level and the travel traffic congestion level of the exited link.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 15, 2014
    Assignee: Aisin AW Co., Ltd.
    Inventors: Takayuki Miyajima, Satoshi Hirano, Kiyokazu Okada
  • Patent number: 8600673
    Abstract: A driving assistance apparatus is configured such that, in a case in which determination has been made there is a road marking within a predetermined range from a vehicle, the road marking is detected based upon an image acquired by a rear-side camera. In a case in which there is a single control target solely associated with the road marking thus detected, or in a case in which there are multiple control targets associated with the road marking, and the difference in the marking-target distance is equal to or greater than a driving control threshold distance, the target-vehicle distance, which is the distance between the vehicle and the control target that is a target for guidance and vehicle control, is calculated. The driving assistance apparatus performs guidance and vehicle control according to the control target based upon the target-vehicle distance thus calculated.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: December 3, 2013
    Assignees: Aisin Aw Co., Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Masaki Nakamura, Naoto Miura, Kiyokazu Okada
  • Publication number: 20130253811
    Abstract: Devices, methods, and programs access map information including link information related to links that constitute a road, acquire a current location of a vehicle at unit time intervals, and acquire traffic information, which includes a distributed traffic congestion level of each link at predetermined time intervals. Each time the vehicle exits a link, the devices, methods, and programs sequentially store the exited link in an exited link train based on the map information. If the traffic information has been received, the devices, methods, and program store the distributed traffic congestion level included in the received traffic information as a traffic congestion level in association with a portion of the exited link train within a range from the current location at a received time point when the traffic information has been received to a location that is a predetermined distance behind the current location at the received time point.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 26, 2013
    Applicant: AISIN AW CO., LTD.
    Inventors: Takayuki MIYAJIMA, Satoshi HIRANO, Kiyokazu OKADA
  • Publication number: 20130253810
    Abstract: Devices, methods, and programs determine whether a vehicle has exited a link based on map information. If so, the devices, methods, and programs acquire a travel traffic congestion level of the exited link based on travel information within the exited link, and determine whether the travel traffic congestion level of the exited link coincides with a distributed traffic congestion level at a time when the vehicle exited. If not, the devices, methods, and programs determine whether the traffic information has been updated and the distributed traffic congestion level has been changed within the exited link, and if so, acquire a distribution time rate of each distributed traffic congestion level within the exited link. The devices, methods, and programs determine a traffic congestion level of the exited link based on the distribution time rate of each acquired distributed traffic congestion level and the travel traffic congestion level of the exited link.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 26, 2013
    Applicant: AISIN AW CO., LTD
    Inventors: Takayuki MIYAJIMA, Satoshi HIRANO, Kiyokazu OKADA
  • Patent number: 8510038
    Abstract: A route guidance system includes: a current position detecting unit; a display condition determination processing unit that determines, for each of pieces of lane data that correspond to a lane list display section set in a forward direction of a vehicle position, whether a display condition for creating a lane list is satisfied, based on the pieces of lane data; a display setting processing unit that sets a piece of the lane data that satisfies the display condition as a display target; and a list display processing unit that displays the lane list based on the piece of the lane data that has been set as the display target. Thus, the piece of the lane data that satisfies the display condition is set as the display target, and the lane list is displayed based on the piece of the lane data that has been set as the display target. Consequently, the size of the lane list can be prevented from becoming too large.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: August 13, 2013
    Assignees: Aisin AW Co., Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Daisuke Tanizaki, Kiyohide Kato, Kenichi Murata, Kiyokazu Okada
  • Patent number: 8452101
    Abstract: A feature extraction method includes: the step of grouping a cluster of features, in which an internal of the respective features is less than or equal to a predetermined grouping interval, to form a feature group, for a plurality of features of which feature information including at least information of a position and a feature type is included in a predetermined feature information storage unit; the step of excluding the feature, not suitable for use in an image recognition process of the feature with respect to image information, from the cluster of the features within the feature group; and the step of extracting a part or all of one or more of the features within the feature group remaining as a result of the exclusion step as a target feature suitable for the use in the image recognition process.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: May 28, 2013
    Assignees: Aisin AW Co., Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Masaki Nakamura, Tomoaki Ishikawa, Koichi Nakao, Motoki Kanba, Osamu Aisaka, Kiyokazu Okada
  • Patent number: 8346473
    Abstract: A lane determining device includes: a feature information obtaining unit for obtaining feature information F of a target feature existing in each lane in the traveling direction of a vehicle 30, based on vehicle position information; an image recognizing unit for conducting image recognition processing of a feature type of the target feature in a vehicle lane, with respect to image information; and a lane accuracy determining unit for determining a vehicle lane accuracy for the respective lanes based on a type of a recognized feature fa shown in an image recognition result, feature types Ft1 to Ft4 of the target feature of the respective lanes shown in the feature information F, in accordance with a level of probability for each of the feature types Ft1 to Ft4 of the target feature of the respective lanes is recognized as the type of the recognized feature fa.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: January 1, 2013
    Assignees: Aisin AW Co., Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Masaki Nakamura, Tomoaki Ishikawa, Koichi Nakao, Osamu Aisaka, Motoki Kanba, Kiyokazu Okada
  • Patent number: 8288855
    Abstract: A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: October 16, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taku Nishiyama, Naohisa Okumura, Kiyokazu Okada
  • Patent number: 8271174
    Abstract: An accuracy error for measuring the position of an own vehicle is calculated based on the information of an execution history of map matching and the information of an update history of a map database. In addition, a predetermined map is referred to based on the calculated accuracy error, and an accuracy error level for performing positioning is specified from among plural stepwise levels. Then, the control level of assist control executed according to the position of the own vehicle is changed so as to correspond to the specified accuracy error level.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: September 18, 2012
    Assignees: Toyota Jidosha Kabushiki Kaisha, Aisin Aw Co., Ltd.
    Inventors: Kiyokazu Okada, Motohiro Nakamura, Hidenobu Suzuki, Masaki Nakamura, Makoto Hasunuma
  • Patent number: 8140266
    Abstract: Based on positioning accuracy of an own vehicle required for appropriately carrying out assistance control carried out according to a position of the own vehicle, an execution condition for map matching correcting the position of the own vehicle is set. Specifically, setting is made in such a manner that, as the positioning accuracy is higher and an error thereof is smaller, an execution frequency of map matching becomes higher. Then, map matching is carried out according to the thus-set execution condition.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: March 20, 2012
    Assignees: Toyota Jidosha Kabushiki Kaisha, Aisin AW Co., Ltd.
    Inventors: Motohiro Nakamura, Kiyokazu Okada, Hidenobu Suzuki, Masaki Nakamura, Makoto Hasunuma
  • Publication number: 20120043671
    Abstract: A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.
    Type: Application
    Filed: November 3, 2011
    Publication date: February 23, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taku NISHIYAMA, Naohisa Okumura, Kiyokazu Okada
  • Patent number: 8110434
    Abstract: A circuit board has a curved portion provided in at least one side of an external shape thereof. An external connecting terminal is provided on a first main surface of the circuit board. A semiconductor element is mounted on a second main surface of the circuit board. A first wiring network is provided in a region except the terminal region on the first main surface. A second wiring network is provided on the second main surface. Distance from the side including the curved portion to the first wiring network is larger than distance from at least one of the other sides to the first wiring networks, and distance from the side including the curved portion to the second wiring network is larger than distance from at least one of the other sides to the second wiring networks.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: February 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Okada, Kiyokazu Okada, Akinori Ono, Taku Nishiyama
  • Patent number: 8080868
    Abstract: A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: December 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taku Nishiyama, Naohisa Okumura, Kiyokazu Okada
  • Patent number: 8064206
    Abstract: A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taku Nishiyama, Kiyokazu Okada, Yoriyasu Ando, Tetsuya Yamamoto, Naohisa Okumura
  • Patent number: 7952183
    Abstract: A element group includes a plurality of semiconductor elements stacked in a step-like shape on a wiring board. The semiconductor elements are electrically connect to connection pads of the wiring board through metal wires. Among the plural semiconductor elements stacked in a step-like shape, the uppermost semiconductor element has a thickness larger than that of the semiconductor element immediately below it.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: May 31, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Okada, Kiyokazu Okada
  • Patent number: 7944037
    Abstract: A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: May 17, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taku Nishiyama, Tetsuya Yamamoto, Kiyokazu Okada
  • Publication number: 20110110053
    Abstract: A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.
    Type: Application
    Filed: January 20, 2011
    Publication date: May 12, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Taku Nishiyama, Kiyokazu Okada, Yoriyasu Ando, Tetsuya Yamamoto, Naohisa Okumura