Patents by Inventor Kiyoko Ikeuchi

Kiyoko Ikeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having trench capacitor structure integrated therein
    Patent number: 9608130
    Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate. The substrate includes multiple capacitor regions, such as a first capacitor region and a second capacitor region that are adjacent to one another. Each capacitor region includes trenches that are formed within the substrate. A metal-insulator-metal capacitor is formed within the trenches and at least partially over the substrate. The trenches disposed within the first capacitor region are at least substantially perpendicular to the trenches disposed within the second capacitor region.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 28, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Khanh Tran, Joseph P. Ellul, Edward M. Godshalk, Kiyoko Ikeuchi, Anuranjan Srivastava
  • Semiconductor device having capacitor integrated therein
    Patent number: 9520462
    Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: December 13, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Khanh Tran, Joseph P. Ellul, Anuranjan Srivastava, Kiyoko Ikeuchi, Scott W. Barry
  • Semiconductor device having capacitor integrated therein
    Patent number: 9196672
    Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: November 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Khanh Tran, Joseph P. Ellul, Anuranjan Srivastava, Kiyoko Ikeuchi, Scott W. Barry
  • Gate etch process
    Patent number: 7112834
    Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: September 26, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Benjamin Schwarz, Chan-Lon Yang, Kiyoko Ikeuchi, Peter Keswick, Lien Lee
  • Gate etch process
    Patent number: 6699795
    Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: March 2, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Benjamin Schwarz, Chan-Lon Yang, Kiyoko Ikeuchi, Peter Keswick, Lien Lee