Patents by Inventor Kiyomi Hagihara

Kiyomi Hagihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8513818
    Abstract: A semiconductor device includes a semiconductor chip having an element formation surface on which at least one element is formed and including a plurality of electrode pads formed on the element formation surface, an interconnect substrate having a principal surface facing the element formation surface of the semiconductor chip and including a plurality of connection pads formed at positions of the principal surface facing the respective corresponding electrode pads, and a plurality of solder bumps provided between the respective corresponding electrode pads and connection pads, and configured to electrically connect the respective corresponding electrode pads and connection pads together. An UBM layer is formed on a portion of each solder bump closer to the corresponding electrode pad and a barrier metal layer is formed on a portion of each solder bump closer to the corresponding connection pad, and the two layers have substantially the same composition of major materials.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: August 20, 2013
    Assignee: Panasonic Corporation
    Inventor: Kiyomi Hagihara
  • Patent number: 8508051
    Abstract: A semiconductor device includes a semiconductor substrate 1, an interlayer insulating film 2, 3 formed on the semiconductor substrate 1, an electrode pad 4 formed on the interlayer insulating film 2, 3, a protective film 6 which is formed on the interlayer insulating film 2, 3 to cover a peripheral portion of the electrode pad 4, and has a first opening 5 which exposes a center portion of the electrode pad 4, a divider 7 which is formed on the electrode pad 4 exposed from the first opening 5, and divides the first opening 5 into a plurality of second openings 5d, and a barrier metal 8 formed on the protective film 6 to fill the second openings 5d. The divider 7 is interposed between the electrode pad 4 and the barrier metal 8.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: August 13, 2013
    Assignee: Panasonic Corporation
    Inventors: Noriyuki Nagai, Kiyomi Hagihara
  • Patent number: 8324740
    Abstract: A semiconductor device includes a multilayer wiring board and a semiconductor chip mounted on the multilayer wiring board. Electrode pads of the semiconductor chip include: first electrode pads including electrode pads respectively disposed in the vicinity of corners of the back surface of the semiconductor chip; and second electrode pads other than the first electrode pads. Connection pads of the multilayer wiring board include: first connection pads connected to the first electrode pads via bumps; and second connection pads connected to the second electrode pads via bumps. The first connection pads are supported by a first insulating region made of a thermoplastic resin, and the second connection pads are supported by a second insulating region made of a thermosetting resin.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: December 4, 2012
    Assignee: Panasonic Corporation
    Inventor: Kiyomi Hagihara
  • Publication number: 20110316153
    Abstract: A semiconductor device includes a semiconductor substrate 1, an interlayer insulating film 2, 3 formed on the semiconductor substrate 1, an electrode pad 4 formed on the interlayer insulating film 2, 3, a protective film 6 which is formed on the interlayer insulating film 2, 3 to cover a peripheral portion of the electrode pad 4, and has a first opening 5 which exposes a center portion of the electrode pad 4, a divider 7 which is formed on the electrode pad 4 exposed from the first opening 5, and divides the first opening 5 into a plurality of second openings 5d, and a barrier metal 8 formed on the protective film 6 to fill the second openings 5d. The divider 7 is interposed between the electrode pad 4 and the barrier metal 8.
    Type: Application
    Filed: September 2, 2011
    Publication date: December 29, 2011
    Applicant: Panasonic Corporation
    Inventors: Noriyuki NAGAI, Kiyomi Hagihara
  • Publication number: 20110147927
    Abstract: A semiconductor device includes a semiconductor chip having an element formation surface on which at least one element is formed and including a plurality of electrode pads formed on the element formation surface, an interconnect substrate having a principal surface facing the element formation surface of the semiconductor chip and including a plurality of connection pads formed at positions of the principal surface facing the respective corresponding electrode pads, and a plurality of solder bumps provided between the respective corresponding electrode pads and connection pads, and configured to electrically connect the respective corresponding electrode pads and connection pads together. An UBM layer is formed on a portion of each solder bump closer to the corresponding electrode pad and a barrier metal layer is formed on a portion of each solder bump closer to the corresponding connection pad, and the two layers have substantially the same composition of major materials.
    Type: Application
    Filed: March 2, 2011
    Publication date: June 23, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Kiyomi HAGIHARA
  • Publication number: 20100140800
    Abstract: A semiconductor device includes a multilayer wiring board and a semiconductor chip mounted on the multilayer wiring board. Electrode pads of the semiconductor chip include: first electrode pads including electrode pads respectively disposed in the vicinity of corners of the back surface of the semiconductor chip; and second electrode pads other than the first electrode pads. Connection pads of the multilayer wiring board include: first connection pads connected to the first electrode pads via bumps; and second connection pads connected to the second electrode pads via bumps. The first connection pads are supported by a first insulating region made of a thermoplastic resin, and the second connection pads are supported by a second insulating region made of a thermosetting resin.
    Type: Application
    Filed: February 18, 2010
    Publication date: June 10, 2010
    Applicant: PANASONIC CORPORATION
    Inventor: Kiyomi Hagihara
  • Publication number: 20100065318
    Abstract: A circuit board according to an embodiment of the present invention relates to a circuit board 2 including an insulating layer 7 and a via conductor 8 embedded in the insulating layer 7. The via conductor 8 has a narrowed portion 80 inclined with respect to a horizontal direction X.
    Type: Application
    Filed: November 27, 2007
    Publication date: March 18, 2010
    Applicant: KYOCERA CORPORATION
    Inventors: Tadashi Nagasawa, Kiyomi Hagihara, Katsura Hayashi