Patents by Inventor Kiyoshi Hayase

Kiyoshi Hayase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11531579
    Abstract: A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: December 20, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kiyoshi Hayase, Shinichi Shibahara, Yuki Hayakawa, Yoichi Yuyama
  • Patent number: 11500708
    Abstract: A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: November 15, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kiyoshi Hayase, Shinichi Shibahara, Yuki Hayakawa, Yoichi Yuyama
  • Publication number: 20220027225
    Abstract: A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Kiyoshi HAYASE, Shinichi SHIBAHARA, Yuki HAYAKAWA, Yoichi YUYAMA
  • Publication number: 20210334152
    Abstract: A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 28, 2021
    Inventors: Kiyoshi HAYASE, Shinichi SHIBAHARA, Yuki HAYAKAWA, Yoichi YUYAMA
  • Publication number: 20040163012
    Abstract: A multiprocessor system is obtained which is capable of efficiently debugging a plurality of processors, while allowing cost reduction. A chip (1) has CPUs (70, 71), debug executing units (80, 81), TAP controllers (90, 91), a selecting circuit (10), and a single set of terminals including terminals (2) to (6). When only the CPU (70) is to be debugged, a TAP controller (100) sets a register (101) so that a signal (S11) is “H” and a signal (S12) is “L.” When only the CPU (71) is to be debugged, the TAP controller (100) sets the register (101) so that the signal (S11) is “L” and the signal (S12) is “H.” When both CPUs (70) and (71) are to be debugged, the TAP controller (100) sets the register (101) so that the signals (S11) and (S12) are both “H.
    Type: Application
    Filed: September 5, 2003
    Publication date: August 19, 2004
    Applicant: Renesas Technology Corp.
    Inventor: Kiyoshi Hayase
  • Publication number: 20030192034
    Abstract: A comparator generates an event A when a value of a PC of a CPU matches a target address set in a target address register. If a trace is performed in a real-time trace mode in the initial state, an RS-FF is set by the generation of the event A and the trace will be performed in a full trace mode. Therefore, by setting a starting address of a subroutine for debugging in the target address register, the trace mode will be changed to the full trace mode when the CPU executes the subroutine, and thereby loss of trace information which will be important in debugging software can be prevented.
    Type: Application
    Filed: December 4, 2002
    Publication date: October 9, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Kiyoshi Hayase
  • Patent number: 6259293
    Abstract: Delay circuitry includes a phase-locked loop or PLL for comparing the phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to the phase difference between the phases of the reference clock and other clock, for generating the other clock using at least a plurality of delay elements connected into a loop, a time delay provided by each of the plurality of delay elements being controlled by the control signal, and for changing the value of the control signal so that the other clock is made to be in phase with the reference clock.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: July 10, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kiyoshi Hayase, Kouichi Ishimi