Patents by Inventor Kiyoshi Maeda

Kiyoshi Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11365075
    Abstract: A sheet accommodating apparatus includes a loading portion onto which a sheet is loaded, a lifting and lowering unit that lifts and lowers the loading portion, a raising portion that raises a sheet loading surface with respect to a lowermost lowering position of the loading portion and above which a portion of the sheet is loaded, and an extension portion that extends to a position outward of the loading portion from the raising portion side as seen in plan view and supports another portion of the sheet.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: June 21, 2022
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Yoshiki Kimura, Kiyoshi Watanabe, Shoichi Maeda, Masashi Ikeda
  • Patent number: 11366507
    Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: June 21, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shuhei Maeda, Shuhei Nagatsuka, Tatsuya Onuki, Kiyoshi Kato
  • Publication number: 20210028356
    Abstract: An etching method includes: preparing a workpiece including a metal multilayer film having a magnetic tunnel junction and a mask formed by an inorganic material on the metal multilayer film; and etching the metal multilayer film by plasma of a mixed gas of ethylene gas and oxygen gas using the mask.
    Type: Application
    Filed: March 15, 2019
    Publication date: January 28, 2021
    Inventors: Ken ANDO, Hiroki MAEHARA, Jun SATO, Kiyoshi MAEDA, Shigeru TAHARA
  • Patent number: 10685816
    Abstract: A method MT includes etching a wafer W using plasma generated in a processing container. The etching includes a process of inclining and rotating a holding structure holding the wafer W during execution of the etching and the process successively creating a plurality of inclined rotation states RT(?, t) with respect to the holding structure. In the inclined rotation states, the wafer W is rotated about a central axis of the wafer W over a predetermined process time while maintaining a state where the central axis is inclined with respect to a reference axis of the processing container which is in the same plane as the central axis. A combination of a value ? of an inclination angle AN of the central axis with respect to the reference axis and the process time t differs for each of the plurality of inclined rotation states.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: June 16, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihiro Umezawa, Jun Sato, Kiyoshi Maeda, Mitsunori Ohata, Kazuya Matsumoto
  • Publication number: 20180337025
    Abstract: A method MT includes etching a wafer W using plasma generated in a processing container. The etching includes a process of inclining and rotating a holding structure holding the wafer W during execution of the etching and the process successively creating a plurality of inclined rotation states RT(?, t) with respect to the holding structure. In the inclined rotation states, the wafer W is rotated about a central axis of the wafer W over a predetermined process time while maintaining a state where the central axis is inclined with respect to a reference axis of the processing container which is in the same plane as the central axis. A combination of a value ? of an inclination angle AN of the central axis with respect to the reference axis and the process time t differs for each of the plurality of inclined rotation states.
    Type: Application
    Filed: November 11, 2016
    Publication date: November 22, 2018
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yoshihiro UMEZAWA, Jun SATO, Kiyoshi MAEDA, Mitsunori OHATA, Kazuya MATSUMOTO
  • Patent number: 10020172
    Abstract: There is provided a plasma processing apparatus including a susceptor, having a substrate mounting portion for mounting thereon a substrate; a focus ring including an outer ring and an inner ring; a dielectric ring; a dielectric constant varying device for varying a dielectric constant of the dielectric ring; a grounding body positioned at an outside of the dielectric ring with a gap from a bottom surface of the focus ring; and a controller for controlling a top surface electric potential of the focus ring by controlling a current flowing from the susceptor to the substrate.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: July 10, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsunori Ohata, Hidetoshi Kimura, Kiyoshi Maeda, Jun Hirose, Tsuyoshi Hida
  • Publication number: 20150255255
    Abstract: There is provided a plasma processing apparatus including a susceptor, having a substrate mounting portion for mounting thereon a substrate; a focus ring including an outer ring and an inner ring; a dielectric ring; a dielectric constant varying device for varying a dielectric constant of the dielectric ring; a grounding body positioned at an outside of the dielectric ring with a gap from a bottom surface of the focus ring; and a controller for controlling a top surface electric potential of the focus ring by controlling a current flowing from the susceptor to the substrate.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: Mitsunori Ohata, Hidetoshi Kimura, Kiyoshi Maeda, Jun Hirose, Tsuyoshi Hida
  • Patent number: 9076636
    Abstract: There is provided a plasma processing apparatus including a susceptor 114, having a substrate mounting portion for mounting thereon a substrate, to which a high frequency power is applied; a focus ring 210, disposed to surround the substrate mounted on the substrate mounting portion, including an outer ring 214 having a top surface higher than a top surface of the substrate and an inner ring 212 extending inwardly from the outer ring so as to allow at least a part of the inner ring to be positioned below a periphery of the substrate, the outer ring and the inner ring being formed as a single member; a dielectric ring 220 positioned between the focus ring and the susceptor; a dielectric constant varying device 250 for varying a dielectric constant of the dielectric ring.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: July 7, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsunori Ohata, Hidetoshi Kimura, Kiyoshi Maeda, Jun Hirose, Tsuyoshi Hida
  • Patent number: 9059103
    Abstract: Disclosed is a processing method that removes moisture in a low permittivity film formed on a substrate to be processed which has a damaged layer on the surface thereof while maintaining the specific permittivity or a leakage current value low when the film is subjected to a recovery processing. The method for the recovery processing includes applying, on the damaged layer of the low permittivity film, a first processing gas whose molecules are small sufficient to permeate the inside of the damaged layer of the low permittivity film and which is able to remove the moisture in the damaged layer and a second processing gas which forms a hydrophobic dense reformatted layer on the surface of the damaged layer, thereby allowing the first processing gas and the second processing gas to react with the damaged layer.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: June 16, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Wataru Shimizu, Kiyoshi Maeda, Toshifumi Nagaiwa
  • Publication number: 20120244720
    Abstract: Disclosed is a processing method that removes moisture in a low permittivity film formed on a substrate to be processed which has a damaged layer on the surface thereof while maintaining the specific permittivity or a leakage current value low when the film is subjected to a recovery processing. The method for the recovery processing includes applying, on the damaged layer of the low permittivity film, a first processing gas whose molecules are small sufficient to permeate the inside of the damaged layer of the low permittivity film and which is able to remove the moisture in the damaged layer and a second processing gas which forms a hydrophobic dense reformatted layer on the surface of the damaged layer, thereby allowing the first processing gas and the second processing gas to react with the damaged layer.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 27, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Wataru SHIMIZU, Kiyoshi MAEDA, Toshifumi NAGAIWA
  • Publication number: 20120061351
    Abstract: There is provided a plasma processing apparatus including a susceptor 114, having a substrate mounting portion for mounting thereon a substrate, to which a high frequency power is applied; a focus ring 210, disposed to surround the substrate mounted on the substrate mounting portion, including an outer ring 214 having a top surface higher than a top surface of the substrate and an inner ring 212 extending inwardly from the outer ring so as to allow at least a part of the inner ring to be positioned below a periphery of the substrate, the outer ring and the inner ring being formed as a single member; a dielectric ring 220 positioned between the focus ring and the susceptor; a dielectric constant varying device 250 for varying a dielectric constant of the dielectric ring.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 15, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Mitsunori Ohata, Hidetoshi Kimura, Kiyoshi Maeda, Jun Hirose, Tsuyoshi Hida
  • Publication number: 20050087878
    Abstract: A semiconductor device includes a silicon substrate having a main surface, a memory cell formed on the main surface, and an interlayer insulating film formed on the main surface to cover the memory cell. The interlayer insulating film has a top surface and a peripheral edge. In the interlayer insulating film, grooves are formed to be placed between the memory cell and the peripheral edge, to extend in parallel with the main surface and to extend in a predetermined direction at a spacing with each other, and a groove is formed to diverge from the grooves and to extend in a direction different from the extending direction of the grooves. The semiconductor device further includes metal film filling the grooves. Thus, crack propagation from the peripheral edge to the inside of the interlayer insulating film can surely be prevented to provide a semiconductor device with high reliability.
    Type: Application
    Filed: April 12, 2004
    Publication date: April 28, 2005
    Inventors: Katsuhiro Uesugi, Kiyoshi Maeda, Kenji Tabaru
  • Publication number: 20030064599
    Abstract: In the production of semiconductor devices, when forming a predetermined pattern within a to-be-processed material such as interlayer film, photoresist is first applied over the material, then exposed, and developed, to thereby form a resist film having the predetermined pattern shape on the material. The material is next etched to a predetermined depth through the resist film as a mask. The resist film is removed and then the material is further etched to form the predetermined pattern within the material. Then, an etching stopper film has been formed at a predetermined depth, the etching is continued until the etching reaches the etching stopper film, and then the photoresist is removed. Additionally, an antireflection layer is used as the etching stopper film.
    Type: Application
    Filed: August 9, 2002
    Publication date: April 3, 2003
    Inventors: Ichiro Miki, Takeshi Matsunuma, Kiyoshi Maeda
  • Patent number: 6461977
    Abstract: An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH2F2 and O2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: October 8, 2002
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hiroshi Matsuo, Takuji Oda, Yuichi Yokoyama, Kiyoshi Maeda, Shinya Inoue, Yuji Yamamoto
  • Patent number: 6444515
    Abstract: A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: September 3, 2002
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hiroshi Matsuo, Yuichi Yokoyama, Takuji Oda, Kiyoshi Maeda, Shinya Inoue, Yuji Yamamoto
  • Publication number: 20010019156
    Abstract: A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.
    Type: Application
    Filed: January 18, 2001
    Publication date: September 6, 2001
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Matsuo, Yuichi Yokoyama, Takuji Oda, Kiyoshi Maeda, Shinya Inoue, Yuji Yamamoto
  • Patent number: 6249015
    Abstract: A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: June 19, 2001
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hiroshi Matsuo, Yuichi Yokoyama, Takuji Oda, Kiyoshi Maeda, Shinya Inoue, Yuji Yamamoto
  • Patent number: 5994227
    Abstract: An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH.sub.2 F.sub.2 and O.sub.2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: November 30, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hiroshi Matsuo, Takuji Oda, Yuichi Yokoyama, Kiyoshi Maeda, Shinya Inoue, Yuji Yamamoto
  • Patent number: 5991503
    Abstract: An encoding unit encodes and compresses picture data in a bit map format corresponding to the MPEG method. A packet assembling portion assembles the picture data encoded by the encoding unit as packets in the format corresponding to the MPEG method, and stores the packets to a storing medium. At this point, the packet assembling portion writes an I picture index to a packet that contains at least a part of I picture data. When a special reproducing operation is performed, a data storing unit reads only packets that have the I picture index. A decoding unit decodes only I picture data of picture data contained in packets read from the storing medium and displays the decoded picture data.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: November 23, 1999
    Assignee: Fujitsu Limited
    Inventors: Hideki Miyasaka, Hideaki Watanabe, Takehira Masanori, Kiyoshi Maeda, Masao Mutou, Hirohiko Inagaki
  • Patent number: 5679204
    Abstract: Components such as an earth plate, a gas introduction ring, and the like placed in a reaction chamber in a plasma apparatus are made of aluminum containing magnesium in a concentration of 2.2 to 2.8% by weight and are not coated with alumite. In addition, a heater incorporated in a section of the reaction chamber heats the section during a plasma cleaning process. Further, an electrical discharge chamber is also incorporated in the plasma apparatus for providing a plasma to the reaction chamber for efficient plasma cleaning of the apparatus.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: October 21, 1997
    Assignees: Shikoku Instrumentation Co., Ltd., Ryoden Semiconductor System Engineering Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masayuki Kobayashi, Kiyoshi Maeda, Masato Toyota, Hiroshi Ohnishi, Hiroshi Tanaka, Toshio Komemura, Tamio Matsumura