Patents by Inventor Kiyoshi Mitani

Kiyoshi Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8703580
    Abstract: In a manufacturing method for manufacturing a silicon on insulator (SOI) wafer, an ion injection layer is formed within the wafer, by injecting a hydrogen ion or a rare gas ion from a surface of the single crystal silicon wafer, the ion injection surface of the single crystal silicon wafer and/or a surface of the transparent insulation substrate is processed using plasma and/or ozone, the ion injection surface of the single crystal silicon wafer is bonded to the surface of the transparent insulation substrate, by bringing them into close contact with each other at room temperature, with the processed surface(s) as bonding surface(s), and an SOI layer is formed on the transparent insulation substrate, by mechanically peeling the single crystal silicon wafer by giving an impact to the ion injection layer.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: April 22, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Atsuo Ito, Yoshihiro Kubota, Kiyoshi Mitani
  • Patent number: 8575722
    Abstract: A method for producing a semiconductor wafer having a multilayer film, in production of a semiconductor device by the steps of forming a porous layer on a surface of a semiconductor wafer by changing a surface portion into the porous layer, forming a semiconductor film on a surface of the porous layer to produce a semiconductor wafer having a multilayer film, fabricating a device on the semiconductor film, and producing the semiconductor device by delaminating the semiconductor film along the porous layer, the semiconductor film having the device formed thereon, including flattening the semiconductor wafer after delaminating and reusing the flattened semiconductor wafer, the method further including a thickness adjusting step of adjusting a whole thickness of the semiconductor wafer having a multilayer film to be produced by reusing the semiconductor wafer so as to satisfy a predetermined standard.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: November 5, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Mitani, Tsuyoshi Ohtsuki, Toru Takahashi, Wei Feig Qu
  • Patent number: 8551246
    Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: October 8, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
  • Patent number: 8236667
    Abstract: Ion injection is performed to a single crystal silicon wafer to form an ion injection layer, with the ion injection surface of the single crystal silicon wafer and/or the surface of the transparent insulation substrate are/is processed using plasma and/or ozone. The ion injection surface of the single crystal silicon wafer and the surface of the transparent insulation substrate are bonded to each other by bringing them into close contact with each other at room temperature. A silicon on insulator (SOI) wafer is obtained by mechanically peeling the single crystal silicon wafer by giving an impact to the ion injection layer, to form an SOI layer on the transparent insulation substrate, and thermal processing for flattening the SOI layer surface is performed to the SOI wafer, under an atmosphere of an inert gas, a hydrogen gas, and a mixture gas of them.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: August 7, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Atsuo Ito, Yoshihiro Kubota, Kiyoshi Mitani
  • Publication number: 20110266655
    Abstract: A method for producing a semiconductor wafer having a multilayer film, in production of a semiconductor device by the steps of forming a porous layer on a surface of a semiconductor wafer by changing a surface portion into the porous layer, forming a semiconductor film on a surface of the porous layer to produce a semiconductor wafer having a multilayer film, fabricating a device on the semiconductor film, and producing the semiconductor device by delaminating the semiconductor film along the porous layer, the semiconductor film having the device formed thereon, including flattening the semiconductor wafer after delaminating and reusing the flattened semiconductor wafer, the method further including a thickness adjusting step of adjusting a whole thickness of the semiconductor wafer having a multilayer film to be produced by reusing the semiconductor wafer so as to satisfy a predetermined standard.
    Type: Application
    Filed: December 8, 2009
    Publication date: November 3, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kiyoshi Mitani, Tsuyoshi Ohtsuki, Toru Takahashi, Wei Feig Qu
  • Patent number: 7959731
    Abstract: A method for producing a semiconductor wafer, including epitaxially growing a Si1-XGeX layer (0<X?1) on a surface of a silicon single crystal wafer to be a bond wafer; implanting at least one kind of a hydrogen ion or a rare gas ion through the Si1-XGeX layer and forming an ion-implanted layer inside the bond wafer; contacting and bonding a surface of the Si1-XGeX layer and a surface of a base wafer through an insulator film; then performing delamination at the ion-implanted layer; performing a bonding heat treatment of binding the bonded surfaces; and then removing a Si layer of a delaminated layer transferred to a side of the base wafer by the delamination. Thereby, the method does not cause lattice relaxation in the SiGe layer. Therefore, the method is suitable for production of a semiconductor wafer for high-speed semiconductor devices.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: June 14, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Hiroji Aga, Kiyoshi Mitani
  • Publication number: 20110045246
    Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
    Type: Application
    Filed: May 7, 2009
    Publication date: February 24, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
  • Patent number: 7608548
    Abstract: Disclosed is a method for cleaning a multilayer substrate at least having a silicon single crystal wafer with a SiGe layer epitaxially grown on a surface of the silicon single crystal wafer, where the SiGe layer is an outermost surface of the SiGe layer and then cleaning the multilayer substrate with a first cleaning liquid capable of etching the protective film so that the protective film remains. The protective film prevents roughening of the surface of the SiGe layer while the cleaning is performed. The cleaning is performed. The cleaning is performed so that a thickness of the remaining protective film is from 1 nm to 100 nm.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: October 27, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Kiyoshi Mitani
  • Patent number: 7601613
    Abstract: In a first ion implantation step (a1), a delamination-intended ion implantation layer 3 is formed by implanting ions at a dosage less than a critical dosage from the insulating film 2 side of a bond wafer 1. In an additional function layer deposition step (b2), an additional function layer 4 is deposited on the insulating film 2 of the bond wafer 1. In a second ion implantation step (c1), by implanting ions at a dosage, the delamination-intended ion implantation layer 3 is matured into a delamination ion implantation layer 3?. Thereby, the delamination ion implantation layer is formed by two steps of ion implantation having the additional function layer deposition step therebetween, and therefore non-uniformity of the additional function layer does not influence uniformity of a film thickness of a bonded semiconductor thin layer.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: October 13, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Kiyoshi Mitani
  • Publication number: 20090203167
    Abstract: The present invention provides a method for manufacturing a bonded substrate that is a method for manufacturing a bonded substrate where an active layer wafer is bonded to a support substrate wafer, comprising: a first step of providing a groove on an inner side on a surface of the active layer wafer along an outer peripheral portion over an entire circumference; a second step of determining a surface where the groove is formed as a bonding surface and bonding the active layer wafer to the support substrate wafer; and a third step of reducing a film thickness of the active layer wafer and removing an unbonded portion on an outer side of the groove of the active layer wafer. As a result, there is provided the method for manufacturing a bonded substrate that can simplify processes, avoid breakage, cracks, or particle generation, and manage a shape of an edge portion of an active layer wafer when reducing a film thickness of the active layer wafer.
    Type: Application
    Filed: November 27, 2006
    Publication date: August 13, 2009
    Applicant: Shin-Etsu Handotai Co., Ltd
    Inventor: Kiyoshi Mitani
  • Patent number: 7560313
    Abstract: The present invention provides a SOI wafer produced by an ion implantation delamination method wherein a width of a SOI island region in a terrace portion generated in an edge portion of the SOI wafer where a surface of a base wafer is exposed is narrower than 1 mm and a density of pit-shaped defects having a size of 0.19 ?m or more existing in a surface of a SOI layer detected by a LPD inspection is 1 counts/cm2 or less, and also provides a method for producing the SOI wafer. Thereby, there is provided a SOI wafer produced by an ion implantation delamination method wherein generation of SOI islands generated in delamination can be suppressed and a defect density of LPDs existing in a surface of the SOI wafer can be reduced, and a method for producing the same, so that device failure can be reduced.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: July 14, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Kiyoshi Mitani
  • Patent number: 7550309
    Abstract: The present invention is a method for producing a semiconductor wafer, comprising at least steps of, epitaxially growing a Si1-XGeX layer (0<X<1) on an SOI wafer, forming a Si1-YGeY layer (0?Y<X) on the epitaxially grown Si1-XGeX layer, and then enriching Ge in the epitaxially grown Si1-XGeX layer by an oxidation heat treatment so that the Si1-XGeX layer becomes an enriched SiGe layer, wherein, at least, the oxidation heat treatment is initiated from 950° C. or less under an oxidizing atmosphere, and the oxidation is performed so that the formed Si1-YGeY layer remains during a temperature rise to 950° C. Thereby, there can be provided a method for producing a semiconductor wafer by which the lattice relaxation of the SiGe layer in an SGOI wafer can be sufficiently performed by a heat treatment for a short time and its production cost can be reduced.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: June 23, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Nobuhiko Noto, Kiyoshi Mitani
  • Patent number: 7531425
    Abstract: This invention relates to a method of fabricating a bonded wafer 39 in which a bond wafer 31 and a base wafer 32, both of which are composed of silicon single crystal, are bonded while placing an oxide film 33 in between, and the bond wafer 31 is thinned. Use of modified chemically-etched wafers as both of the bond wafer 31 and base wafer 32 is successful in reducing an unbonded area UA therebetween after annealing for bonding, where the modified chemically-etched wafer refers to a wafer which is etched by alkali etching and succeeding acid etching, while setting etching amount larger in the alkali etching than in the acid etching.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: May 12, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masatake Nakano, Shinichi Tomizawa, Kiyoshi Mitani
  • Patent number: 7524744
    Abstract: The present invention provides a method of producing an SOI wafer, comprising at least steps of forming an oxygen ion-implanted layer by implanting oxygen ions into a silicon wafer from one main surface thereof, subjecting the silicon wafer to oxide film-forming heat treatment to convert the oxygen ion-implanted layer into a buried oxide film, and thereby producing an SOI wafer having an SOI layer on the buried oxide film, wherein when the buried oxide film is formed in the silicon wafer, the buried oxide film is formed so that a thickness thereof is thicker than a thickness of the buried oxide film which the SOI wafer to be produced has, and thereafter the silicon wafer in which the thicker buried oxide film is formed is subjected to a heat treatment to reduce the thickness of the buried oxide film.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: April 28, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Hiroji Aga, Kiyotaka Takano, Kiyoshi Mitani
  • Publication number: 20080305318
    Abstract: In a manufacturing method of manufacturing a silicon on insulator (SOI) wafer, a single crystal silicon whose surface is an N region on an outer side of an OSF region, is grown and sliced to fabricate an N region single crystal silicon. An ion injection layer is formed within the N region single crystal silicon wafer by injecting a hydrogen ion or a rare gas ion from a surface of the N region single crystal silicon wafer; the ion injection surface of the N region single crystal silicon wafer and/or a surface of the transparent insulation substrate is processed using plasma and/or ozone. The ion injection surface is bonded to the surface of the transparent insulation substrate by bringing them into close contact with each other at room temperature. An SOI layer is formed by mechanically peeling the single crystal silicon wafer.
    Type: Application
    Filed: June 27, 2008
    Publication date: December 11, 2008
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Atsuo Ito, Yoshihiro Kubota, Kiyoshi Mitani
  • Publication number: 20080305317
    Abstract: In a manufacturing method for manufacturing a silicon on insulator (SOI) wafer, an ion injection layer is formed within the wafer, by injecting a hydrogen ion or a rare gas ion from a surface of the single crystal silicon wafer, the ion injection surface of the single crystal silicon wafer and/or a surface of the transparent insulation substrate is processed using plasma and/or ozone, the ion injection surface of the single crystal silicon wafer is bonded to the surface of the transparent insulation substrate, by bringing them into close contact with each other at room temperature, with the processed surface(s) as bonding surface(s), and an SOI layer is formed on the transparent insulation substrate, by mechanically peeling the single crystal silicon wafer by giving an impact to the ion injection layer.
    Type: Application
    Filed: June 27, 2008
    Publication date: December 11, 2008
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: ATSUO ITO, YOSHIHIRO KUBOTA, KIYOSHI MITANI
  • Publication number: 20080299376
    Abstract: Ion injection is performed to a single crystal silicon wafer to form an ion injection layer, with the ion injection surface of the single crystal silicon wafer and/or the surface of the transparent insulation substrate are/is processed using plasma and/or ozone. The ion injection surface of the single crystal silicon wafer and the surface of the transparent insulation substrate are bonded to each other by bringing them into close contact with each other at room temperature. A silicon on insulator (SOI) wafer is obtained by mechanically peeling the single crystal silicon wafer by giving an impact to the ion injection layer, to form an SOI layer on the transparent insulation substrate, and thermal processing for flattening the SOI layer surface is performed to the SOI wafer, under an atmosphere of an inert gas, a hydrogen gas, and a mixture gas of them.
    Type: Application
    Filed: June 27, 2008
    Publication date: December 4, 2008
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: ATSUO ITO, YOSHIHIRO KUBOTA, KIYOSHI MITANI
  • Publication number: 20080286937
    Abstract: In a first ion implantation step (a1), a delamination-intended ion implantation layer 3 is formed by implanting ions at a dosage less than a critical dosage from the insulating film 2 side of a bond wafer 1. In an additional function layer deposition step (b2), an additional function layer 4 is deposited on the insulating film 2 of the bond wafer 1. In a second ion implantation step (c1), by implanting ions at a dosage, the delamination-intended ion implantation layer 3 is matured into a delamination ion implantation layer 3?. Thereby, the delamination ion implantation layer is formed by two steps of ion implantation having the additional function layer deposition step therebetween, and therefore non-uniformity of the additional function layer does not influence uniformity of a film thickness of a bonded semiconductor thin layer.
    Type: Application
    Filed: June 6, 2005
    Publication date: November 20, 2008
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventor: Kiyoshi Mitani
  • Publication number: 20080138959
    Abstract: The present invention is a method for producing a semiconductor wafer, comprising: at least epitaxially growing a Si1-XGeX layer (0<X?1) on a surface of a silicon single crystal wafer to be a bond wafer; implanting at least one kind of a hydrogen ion or a rare gas ion through the Si1-XGeX layer and thereby, forming an ion-implanted layer inside the bond wafer; closely contacting and bonding a surface of the Si1-XGeX layer and a surface of a base wafer through an insulator film; then performing a delamination treatment of performing delamination at the ion-implanted layer; performing a bonding heat treatment of binding the bonded surfaces at a temperature of, at least, more than or equal to a temperature when the delamination treatment is performed; and then removing a Si layer of a delaminated layer transferred to a side of the base wafer by the delamination.
    Type: Application
    Filed: November 2, 2005
    Publication date: June 12, 2008
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Hiroji Aga, Kiyoshi Mitani
  • Patent number: 7320929
    Abstract: In order to adjust thickness of a bonded silicon single crystal film 15 depending of thickness of an SOI layer 5 to be obtained, depth of formation d1+tx of a separatory ion implanted layer 4, measured from a first main surface J, in the separatory ion implanted layer formation step is adjusted through energy of the ion implantation. Dose of the ion implantation is set smaller as the depth of formation measured from the first main surface J becomes smaller. A smaller dose results in a smaller surface roughness of the separation surface, and makes it possible to reduce polishing stock removal of the separation surface of the bonded silicon single crystal film in the planarization step. Uniformity in the thickness of the SOI layer can consequently be improved even for the case where a thin SOI layer has to be formed.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: January 22, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Kiyoshi Mitani