Abstract: A method of manufacturing a bonding substrate is disclosed. An oxide film is formed on the surface of at least one of two semiconductor substrates, and the two substrates are brought into close contact with each other via the oxide film. The substrates are heat-treated in an oxidizing atmosphere in order to firmly join the substrates together. Subsequently, an unjoined portion at the periphery of a device-fabricating substrate is completely removed, and the thickness of the device-fabricating substrate is reduced to a desired thickness so as to yield a thin film. The surface of the thin film is then etched through vapor-phase etching in order to make the thickness of the thin film uniform. In the method, the oxide film on the unjoined portion of at least the support substrate is removed before the surface of the thin film is subjected to vapor-phase etching.

Abstract: A method of fabricating a bonded wafer which is capable of reducing the concentrations of impurities, and more particularly the boron concentration, at the interface of bonding in the bonded wafer, wherein first and second wafers to be bonded are finish-cleaned, then the wafers are temporarily stored in a closed box so as to isolate the wafers from clean-room air, thereafter the first and second wafers are superposed in a clean atmosphere which is held out of direct contact with clean-room air, and finally the superposed first and second wafers are bonded together by a heat-treatment.

Abstract: The present invention is a CMOS epitaxial semiconductor wafer (50) on which CMOS integrated circuits (16) can be manufactured, including such circuits that include bipolar components (referred to as "BiCMOS" circuits). The CMOS wafer includes a lightly doped monocrystalline silicon substrate (56) having a major surface (54) that supports a lightly doped monocrystalline epitaxial silicon layer (52). The substrate includes a heavily doped diffused layer (58) extending a short distance (64) into the substrate from the major surface toward a lightly doped bulk portion (66) of the substrate. CMOS integrated circuits manufactured on the epitaxial layer of the CMOS wafer of this invention have a low susceptibility to latch-up. The low susceptibility is provided by the relatively low resistivity of the diffused layer. Since the diffused layer is relatively thin and the bulk portion is lightly doped, the oxygen content of the bulk can be readily measured and controlled.

Abstract: SOI (silicon-on-insulator) substrates are efficiently produced by a method which comprises superposing and bonding at least three single crystal silicon wafers through the medium of a SiO.sub.2 film formed on the surface of each of the wafers and cutting the bonded wafers along planes perpendicular to the direction of superposition thereof. The cutting can be infallibly attained with high dimensional accuracy without entailing such adverse phenomena as the vibration of the blade of a cutting tool by providing at the portions destined to be cut the grooves for guiding the blade of the cutting tool in advance of the cutting work.

Abstract: A method for the determination of the resistivity of an n-type epitaxial layer formed on a silicon substrate is disclosed. This invention resides in either directly determining the true resistivity of a sample by preparing this sample without a natural oxide film which is responsible for the change with the passage of time or indirectly determining the true resistivity of a sample by intentionally forming on the sample a natural oxide film so stable to defy the change with the passage of time and measuring resistivity of this sample.

Abstract: A method of estimating the amount of boron on the surface of silicone samples in which a plurality of reference samples shallowly ion-implanted with boron in different dosages are prepared and heat-treated under the same conditions of temperature and time as are used in a bonding heat treatment to obtain the bonded wafer, thereafter, the boron profile in the direction of the depth of the bonding interface in each reference sample is measured using a SIMS and compared with an actual boron profile at the bonding interface of a bonded wafer to be estimated so as to determine one reference sample whose boron profile is equivalent to the actual boron profile of the bonded wafer to be estimated, and finally a dosage of boron in the determined reference sample is estimated by convertion to be a surface density of boron presenting at the bonding interface of the bonded wafer to be estimated at an initial stage prior to the bonding heat treatment of the bonded wafer to be estimated.

Abstract: A method is disclosed for obtaining bonded wafers of SOI type, where impurity redistribution in the bulk of the wafers is suppressed and the bonding strength between the wafers is substantially higher compared with that in the prior art. This is accomplished by forming a thermally grown oxide layer on the surface of the thinner one(bond wafer) of two monocrystalline silicon wafers having thicknesses different from each other by more than 50 .mu.m; then superposing the thinner wafer onto the other thicker wafer(base wafer); and finally conducting at least two heat treatments of the wafers at temperatures selected in the range of under 900.degree. C. for a period of time selected in the range of from 0.5 min. to 120 min.

Abstract: There is provided an SOI (Silicon On Insulator) substrate having a thick SOI layer, where crystallographic defects mainly consisting of OSFs (Oxidation Induced Stacking Fault) are practically prevented from occurrence in the SOI layer, according to the present invention.The manufacturing method for the SOI substrate according to the present invention comprises the following steps of: the silicon oxide film being formed by thermal oxidation on the surface of a first silicon wafer having a concentration of interstitial oxygen under 16 ppma (per JEIDA Standard); the first silicon wafer being superimposed on a second silicon wafer, which is a support for supporting the first silicon wafer, with the silicon oxide film sandwiched therebetween; then the superimposed wafers being heat-treated so as to obtain a bonded wafer; and further the bulk of the first silicon wafer of the bonded wafer being reduced by grinding and then polishing so as to obtain the SOI substrate with the SOI layer of more than 5 .mu.

Abstract: The present invention is a CMOS epitaxial silicon wafer (50) on which CMOS integrated circuits (16) can be manufactured, including such circuits that include bipolar components (referred to as "BiCMOS" circuits). The CMOS wafer includes a lightly doped monocrystalline silicon substrate (56) having a major surface (54) that supports a lightly doped monocrystalline epitaxial silicon layer (52). The substrate includes a heavily doped diffused layer (58) extending a short distance (64) into the substrate from the major surface toward a lightly doped bulk portion (66) of the substrate. CMOS integrated circuits manufactured on the epitaxial layer of the CMOS wafer of this invention have a low susceptibility to latch-up. The low susceptibility is provided by the relatively low resistivity of the diffused layer. Since the diffused layer is relatively thin and the bulk portion is lightly doped, the oxygen content of the bulk can be readily measured and controlled.

Abstract: A hand riveter consisting essentially of a frame main body, a lever, a jaw case support member, a jaw case accommodating a jaw assembly, and a jaw case housing. The jaw assembly attached to the head portion of the riveter is easily shiftable to a forward position or a downward position as desired through an angle of displacement of about 90 degrees.