Patents by Inventor Kiyoshi Umezawa

Kiyoshi Umezawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4626838
    Abstract: An apparatus for filling an interior of a shape to be displayed on a raster scan CRT which reads out a refresh memory. The apparatus includes a memory for storing information of starting points and ending points for filling. The write of a filling color code into the refresh memory is initiated and terminates in response to the filling starting point and the filling ending point, respectively, but inhibited at its memory locations on the contour of the shape. The direction of the filling is perpendicular to the raster scanning of the CRT.
    Type: Grant
    Filed: October 13, 1983
    Date of Patent: December 2, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Tsujioka, Seiichi Kanema, Eiji Okamura, Kiyoshi Umezawa, Mitsuo Ooyama, Toshihisa Aoshima, Mitsugu Yoneyama
  • Patent number: 4580236
    Abstract: A graphic display apparatus for generating a vector comprises registers for storing a value R of a vector discrimination, a positive increment P and a negative increment N, and flip-flops for storing magnitude information of .DELTA.X, .DELTA.Y, and .DELTA.X and .DELTA.Y. An address counter of a refresh memory is counted up or down in accordance with the contents of those flip-flops. A control circuit for updating the value R of the vector discrimination is also provided, so that the vector can be generated at a high speed. The registers and the flip-flops are constructed in two stages so that data for generating the next vector can be prepared while the current vector is generated.
    Type: Grant
    Filed: May 24, 1983
    Date of Patent: April 1, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Tsujioka, Eiji Okamura, Mitsuo Ooyama, Kimiaki Ando, Seiichi Kanema, Mitsugu Yoneyama, Toshihisa Aoshima, Kiyoshi Umezawa
  • Patent number: 4158883
    Abstract: In a refresh control system including a main memory having a volatile memory, at least one processing unit for accessing the main memory, a memory bus for effecting signal transfer between the main memory and the processing unit and a supervision circuit for allotting use of the memory bus in response to a request signal, the refresh control system is characterized by a refresh control circuit for transferring the request signal to the supervision circuit at the time the refresh signal is required and for commanding the initiation of the refresh operation to the main memory in response to a grant signal from the supervision circuit.
    Type: Grant
    Filed: November 1, 1976
    Date of Patent: June 19, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Kadono, Tsuneyo Chiba, Kiyoshi Umezawa