Patents by Inventor Kiyotaka Iwasaki
Kiyotaka Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941251Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.Type: GrantFiled: November 8, 2022Date of Patent: March 26, 2024Assignee: Kioxia CorporationInventors: Yoshihisa Kojima, Masanobu Shirakawa, Kiyotaka Iwasaki
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Publication number: 20240094940Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform a write operation of a first data cluster and a first partial overwrite operation of the first data cluster with first overwrite data. The write operation includes compressing and then encrypting the first data cluster, and writing the compressed and encrypted first data cluster into a first physical location of the non-volatile memory. The first partial overwrite operation includes encrypting the first overwrite data without performing compression, reading the compressed and encrypted first data cluster from the first physical location of the non-volatile memory, generating a first composite data cluster with the compressed and encrypted first data cluster read from the first physical location and the encrypted first overwrite data that is not compressed, and writing the first composite data cluster into a second physical location of the non-volatile memory.Type: ApplicationFiled: September 1, 2023Publication date: March 21, 2024Inventors: Kensaku YAMAGUCHI, Kiyotaka IWASAKI, Takashi TAKEMOTO, Kohei OIKAWA
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Publication number: 20240094947Abstract: According to one embodiment, a system includes: a memory, and a controller, wherein the memory includes a first die including first and second planes and a second die including a third plane, and the controller issues a read command to the first and second dies, if a read time for first data in the first plane has ended, a read time for second data in the second plane has ended after the end of the read time for the first data, and a read time for third data in the third plane has ended after the end of the read time for the second data, receives the first data from the first die, receives the third data from the second die after completion of receiving the first data, and receives the second data from the first die after completion of receiving the third data.Type: ApplicationFiled: June 19, 2023Publication date: March 21, 2024Applicant: Kioxia CorporationInventors: Atsuo SHONO, Kiyotaka IWASAKI
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Publication number: 20230275601Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Applicant: KIOXIA CORPORATIONInventors: Riki SUZUKI, Toshikatsu HIDA, Osamu TORII, Hiroshi YAO, Kiyotaka IWASAKI
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Patent number: 11683053Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: GrantFiled: February 18, 2021Date of Patent: June 20, 2023Assignee: KIOXIA CORPORATIONInventors: Riki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
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Publication number: 20230056583Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.Type: ApplicationFiled: November 8, 2022Publication date: February 23, 2023Applicant: Kioxia CorporationInventors: Yoshihisa KOJIMA, Masanobu SHIRAKAWA, Kiyotaka IWASAKI
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Patent number: 11543969Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, as input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.Type: GrantFiled: May 27, 2021Date of Patent: January 3, 2023Assignee: Kioxia CorporationInventors: Yoshihisa Kojima, Masanobu Shirakawa, Kiyotaka Iwasaki
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Patent number: 11264098Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.Type: GrantFiled: May 1, 2020Date of Patent: March 1, 2022Assignee: KIOXIA CORPORATIONInventors: Shinya Koizumi, Kiyotaka Iwasaki
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Publication number: 20220044738Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.Type: ApplicationFiled: October 27, 2021Publication date: February 10, 2022Applicant: Toshiba Memory CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Kengo KUROSE, Marie TAKADA, Ryo YAMAKI, Kiyotaka IWASAKI, Yoshihisa KOJIMA
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Patent number: 11195585Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.Type: GrantFiled: March 11, 2019Date of Patent: December 7, 2021Assignee: Toshiba Memory CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kengo Kurose, Marie Takada, Ryo Yamaki, Kiyotaka Iwasaki, Yoshihisa Kojima
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Publication number: 20210286524Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, as input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.Type: ApplicationFiled: May 27, 2021Publication date: September 16, 2021Applicant: Toshiba Memory CorporationInventors: Yoshihisa KOJIMA, Masanobu SHIRAKAWA, Kiyotaka IWASAKI
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Patent number: 11114170Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.Type: GrantFiled: May 28, 2020Date of Patent: September 7, 2021Assignee: KIOXIA CORPORATIONInventors: Takaya Handa, Yoshihisa Kojima, Kiyotaka Iwasaki
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Publication number: 20210267467Abstract: An ischemic cardiopathy diagnosis assistance system includes pressure data acquisition means 11 for acquiring pressure data including proximal pressure Pa in a proximal stenotic segment A1 and distal pressure Pd in a distal stenotic segment A2; intracoronary electrocardiogram data acquisition means 12 for acquiring intracoronary electrocardiogram data made up of a local intracoronary artery electrocardiogram in a neighborhood of the distal stenotic segment; and computational processing means 14 for finding a pressure ratio Pa/Pd between the proximal pressure Pa and distal pressure Pd at a time suitable for diagnosis of ischemic cardiopathy based on these data.Type: ApplicationFiled: July 19, 2019Publication date: September 2, 2021Applicant: WASEDA UNIVERSITYInventors: Masafumi Nakayama, Kiyotaka Iwasaki
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Patent number: 11068167Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.Type: GrantFiled: September 4, 2019Date of Patent: July 20, 2021Assignee: Toshiba Memory CorporationInventors: Yoshihisa Kojima, Masanobu Shirakawa, Kiyotaka Iwasaki
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Publication number: 20210175907Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: ApplicationFiled: February 18, 2021Publication date: June 10, 2021Applicant: Toshiba Memory CorporationInventors: Riki SUZUKI, Toshikatsu HIDA, Osamu TORII, Hiroshi YAO, Kiyotaka IWASAKI
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Patent number: 10965324Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: GrantFiled: May 22, 2019Date of Patent: March 30, 2021Assignee: Toshiba Memory CorporationInventors: Riki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
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Patent number: 10929061Abstract: According to one embodiment, a memory system is configured to include a nonvolatile memory and a controller circuit. The controller circuit is electrically connected to the nonvolatile memory. The controller circuit executes a first process and a second process. The first process manages a history of accesses to first storage areas of the nonvolatile memory. The second process manages a progress of accesses to all storage areas of the first storage areas within a first time limit, based on the history of the accesses.Type: GrantFiled: September 11, 2018Date of Patent: February 23, 2021Assignees: TOSHIBA INFORMATION SYSTEMS (JAPAN) CORPORATION, TOSHIBA MEMORY CORPORATIONInventors: Kouji Watanabe, Kiyotaka Iwasaki
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Patent number: 10915266Abstract: According to one embodiment, a storage device includes a first memory cell; a second memory cell; and a controller configured to, in response to receiving a first command set, execute a first erase operation which is included in an erase operation of data of the first memory cell, and suspend the first erase operation, and in response to receiving a second command set, execute a read operation or a write operation of the second memory cell and subsequently resume the suspended first erase operation.Type: GrantFiled: September 16, 2016Date of Patent: February 9, 2021Assignees: TOSHIBA MEMORY CORPORATION, TOSHIBA INFORMATION SYSTEMS (JAPAN) CORPORATIONInventors: Yusuke Ochi, Masanobu Shirakawa, Yoshihisa Kojima, Kiyotaka Iwasaki, Katsuhiko Ueki, Kouji Watanabe
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Publication number: 20200294605Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.Type: ApplicationFiled: May 28, 2020Publication date: September 17, 2020Inventors: Takaya HANDA, Yoshihisa KOJIMA, Kiyotaka IWASAKI
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Publication number: 20200258576Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.Type: ApplicationFiled: May 1, 2020Publication date: August 13, 2020Inventors: Shinya Koizumi, Kiyotaka Iwasaki