Patents by Inventor Kiyotaka Iwasaki

Kiyotaka Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210286524
    Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, as input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 16, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshihisa KOJIMA, Masanobu SHIRAKAWA, Kiyotaka IWASAKI
  • Patent number: 11114170
    Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 7, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Takaya Handa, Yoshihisa Kojima, Kiyotaka Iwasaki
  • Publication number: 20210267467
    Abstract: An ischemic cardiopathy diagnosis assistance system includes pressure data acquisition means 11 for acquiring pressure data including proximal pressure Pa in a proximal stenotic segment A1 and distal pressure Pd in a distal stenotic segment A2; intracoronary electrocardiogram data acquisition means 12 for acquiring intracoronary electrocardiogram data made up of a local intracoronary artery electrocardiogram in a neighborhood of the distal stenotic segment; and computational processing means 14 for finding a pressure ratio Pa/Pd between the proximal pressure Pa and distal pressure Pd at a time suitable for diagnosis of ischemic cardiopathy based on these data.
    Type: Application
    Filed: July 19, 2019
    Publication date: September 2, 2021
    Applicant: WASEDA UNIVERSITY
    Inventors: Masafumi Nakayama, Kiyotaka Iwasaki
  • Patent number: 11068167
    Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 20, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Masanobu Shirakawa, Kiyotaka Iwasaki
  • Publication number: 20210175907
    Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Riki SUZUKI, Toshikatsu HIDA, Osamu TORII, Hiroshi YAO, Kiyotaka IWASAKI
  • Patent number: 10965324
    Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Riki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
  • Patent number: 10929061
    Abstract: According to one embodiment, a memory system is configured to include a nonvolatile memory and a controller circuit. The controller circuit is electrically connected to the nonvolatile memory. The controller circuit executes a first process and a second process. The first process manages a history of accesses to first storage areas of the nonvolatile memory. The second process manages a progress of accesses to all storage areas of the first storage areas within a first time limit, based on the history of the accesses.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 23, 2021
    Assignees: TOSHIBA INFORMATION SYSTEMS (JAPAN) CORPORATION, TOSHIBA MEMORY CORPORATION
    Inventors: Kouji Watanabe, Kiyotaka Iwasaki
  • Patent number: 10915266
    Abstract: According to one embodiment, a storage device includes a first memory cell; a second memory cell; and a controller configured to, in response to receiving a first command set, execute a first erase operation which is included in an erase operation of data of the first memory cell, and suspend the first erase operation, and in response to receiving a second command set, execute a read operation or a write operation of the second memory cell and subsequently resume the suspended first erase operation.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 9, 2021
    Assignees: TOSHIBA MEMORY CORPORATION, TOSHIBA INFORMATION SYSTEMS (JAPAN) CORPORATION
    Inventors: Yusuke Ochi, Masanobu Shirakawa, Yoshihisa Kojima, Kiyotaka Iwasaki, Katsuhiko Ueki, Kouji Watanabe
  • Publication number: 20200294605
    Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Inventors: Takaya HANDA, Yoshihisa KOJIMA, Kiyotaka IWASAKI
  • Publication number: 20200258576
    Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.
    Type: Application
    Filed: May 1, 2020
    Publication date: August 13, 2020
    Inventors: Shinya Koizumi, Kiyotaka Iwasaki
  • Patent number: 10706940
    Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takaya Handa, Yoshihisa Kojima, Kiyotaka Iwasaki
  • Patent number: 10685710
    Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinya Koizumi, Kiyotaka Iwasaki
  • Patent number: 10660977
    Abstract: The present invention suppresses the strength reduction or degeneration of a tissue after the tissue is dried and/or sterilized, for the tissue comprising biological components and the like. Specifically, biological tissue is immersed in a trehalose solution and shaken, thereby impregnating the biological tissue with the trehalose solution. The trehalose solution used here is one obtained by dissolving trehalose in a phosphate buffered saline, the concentration of trehalose being preferably in the range of 20 wt % to 35 wt %. Thereafter, the biological tissue is dried to remove moisture in the biological tissue, and sterilized with ethylene oxide gas.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: May 26, 2020
    Assignee: WASEDA UNIVERSITY
    Inventors: Kiyotaka Iwasaki, Mitsuo Umezu
  • Publication number: 20200089414
    Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 19, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshihisa KOJIMA, Masanobu SHIRAKAWA, Kiyotaka IWASAKI
  • Publication number: 20200090763
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.
    Type: Application
    Filed: March 11, 2019
    Publication date: March 19, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kengo Kurose, Marie Takada, Ryo Yamaki, Kiyotaka Iwasaki, Yoshihisa Kojima
  • Patent number: 10552047
    Abstract: A memory system includes a memory controller comprising n (where n>2) first data input/output terminals, a first semiconductor chip comprising n second data input/output terminals, each of the second data input/output terminals being connected to a respective one of the first data input/output terminals, and a second semiconductor chip comprising n third data input/output terminals, each of the third data input/output terminals being connected to a respective one of the first data input/output terminals. When a first request signal is output from the memory controller, status data of the first semiconductor chip is output from a first of the second data input/output terminals that is connected to a first of the first data input/output terminals, and status data of the second semiconductor chip is output from a second of the third data input/output terminals that is connected to a second of the first data input/output terminals.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuusuke Nosaka, Masanobu Shirakawa, Yoshihisa Kojima, Kiyotaka Iwasaki, Hiroshi Sukegawa
  • Patent number: 10432231
    Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Riki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
  • Publication number: 20190278517
    Abstract: According to one embodiment, a memory system is configured to include a nonvolatile memory and a controller circuit. The controller circuit is electrically connected to the nonvolatile memory. The controller circuit executes a first process and a second process. The first process manages a history of accesses to first storage areas of the nonvolatile memory. The second process manages a progress of accesses to all storage areas of the first storage areas within a first time limit, based on the history of the accesses.
    Type: Application
    Filed: September 11, 2018
    Publication date: September 12, 2019
    Inventors: Kouji WATANABE, Kiyotaka IWASAKI
  • Publication number: 20190273516
    Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
    Type: Application
    Filed: May 22, 2019
    Publication date: September 5, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Riki SUZUKI, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
  • Publication number: 20190198120
    Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.
    Type: Application
    Filed: August 28, 2018
    Publication date: June 27, 2019
    Inventors: Takaya HANDA, Yoshihisa KOJIMA, Kiyotaka IWASAKI