Abstract: A semiconductor device comprises a semiconductor substrate, a connection pad, and a bump. The connection pad is connected to the bump and disposed between the semiconductor substrate and the bump. The connection pad has one or more slits.

Abstract: Provided is a technique for promoting miniaturization of a MISFET. A p-type well region is disposed between LDDs (n-type low-concentration regions) of a MISFET (Qn) to cause both the well region and the low-concentration region to partially overlap each other, whereby an overlap region formed of an n-type semiconductor region having a higher resistance than that of the n-type low-concentration region is provided between the p-type well region and each of the n-type low-concentration regions. In this way, the overlap region can relieve an electric field concentration at the end of the n-type low-concentration region, thereby suppressing the occurrence of hot carriers without elongating an offset length of the LDD, which can promote the miniaturization of the MISFET (Qn), particularly, that operates at high voltage.

Abstract: Provided is a technique for promoting miniaturization of a MISFET. A p-type well region is disposed between LDDs (n-type low-concentration regions) of a MISFET (Qn) to cause both the well region and the low-concentration region to partially overlap each other, whereby an overlap region formed of an n-type semiconductor region having a higher resistance than that of the n-type low-concentration region is provided between the p-type well region and each of the n-type low-concentration regions. In this way, the overlap region can relieve an electric field concentration at the end of the n-type low-concentration region, thereby suppressing the occurrence of hot carriers without elongating an offset length of the LDD, which can promote the miniaturization of the MISFET (Qn), particularly, that operates at high voltage.

Abstract: On a silicon substrate 120 of a semiconductor device, a field oxide film 101 is provided. On the field oxide film 101, two fuses 104 are provided. Directly below the fuses 104 in the silicon substrate 120, an n-type well 102 is provided. Besides the n-type well 102, a p-type well 103 is provided in such a manner as to surround a region directly under the fuses 104 in the silicon substrate 120. A cover insulating film 108 is provided over the silicon substrate 120 and the field oxide film 101. A seal ring composed of a contact 106 and an interconnection 107 is embedded in the cover insulating film 108 so as to surround the fuses 104.

Abstract: On a silicon substrate 120 of a semiconductor device, a field oxide film 101 is provided. On the field oxide film 101, two fuses 104 are provided. Directly below the fuses 104 in the silicon substrate 120, an n-type well 102 is provided. Besides the n-type well 102, a p-type well 103 is provided in such a manner as to surround a region directly under the fuses 104 in the silicon substrate 120. A cover insulating film 108 is provided over the silicon substrate 120 and the field oxide film 101. A seal ring composed of a contact 106 and an interconnection 107 is embedded in the cover insulating film 108 so as to surround the fuses 104.

Abstract: The invention provides a method for manufacturing a semiconductor device, reducing the number of processes in a self-alignment metal damascene gate process. The invention deposits a silicon nitride film on a semiconductor substrate, selectively removes the silicon nitride film and the semiconductor substrate to form a trench groove, and deposits a first insulating film all over the semiconductor substrate so as to fill up the trench groove with it. Following this, the invention removes this first insulating film to expose said silicon nitride film and selectively removes the exposed silicon nitride film to form a dummy gate electrode.

Abstract: In a method for forming a device isolation region of an STI structure in a semiconductor device, a surface protecting oxide film is formed on the surface of a trench by a thermal oxidation. Thereafter, a first silicon oxide film is deposited on the whole surface to fill up the trench and to cover the silicon nitride film on the principal surface of the silicon substrate, and then, by using the silicon nitride film as a stopper, a first CMP process is carried so that the first silicon oxide film remains in the trench. Thereafter, the silicon nitride film is removed, and a HTO film is formed on the pad oxide film covering the principal surface of the silicon substrate. Then, a second silicon oxide film is formed, and furthermore, a second CMP process is carried out to the extent that the principal surface of the silicon substrate is not exposed. Finally, a wet etching is carried so that the device isolation region of the STI structure is formed with no deterioration of the electric characteristics.

Abstract: In a method for forming a device isolation region of an STI structure in a semiconductor device, a surface protecting oxide film is formed on the surface of a trench by a thermal oxidation. Thereafter, a first silicon oxide film is deposited on the whole surface to fill up the trench and to cover the silicon nitride film on the principal surface of the silicon substrate, and then, by using the silicon nitride film as a stopper, a first CMP process is carried so that the first silicon oxide film remains in the trench. Thereafter, the silicon nitride film is removed, and a HTO film is formed on the pad oxide film covering the principal surface of the silicon substrate. Then, a second silicon oxide film is formed, and furthermore, a second CMP process is carried out to the extent that the principal surface of the silicon substrate is not exposed. Finally, a wet etching is carried so that the device isolation region of the STI structure is formed with no deterioration of the electric characteristics.