Patents by Inventor Kiyotaka Seyama
Kiyotaka Seyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7935891Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.Type: GrantFiled: February 14, 2008Date of Patent: May 3, 2011Assignee: Fujitsu LimitedInventors: Takashi Shuto, Kenji Takano, Kenji Iida, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
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Publication number: 20080142256Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.Type: ApplicationFiled: February 14, 2008Publication date: June 19, 2008Applicant: FUJITSU LIMITEDInventors: Takashi Shuto, Kenji Takano, Kenji Iida, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
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Patent number: 7377030Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.Type: GrantFiled: November 4, 2005Date of Patent: May 27, 2008Assignee: Fujitsu LimitedInventors: Takashi Shuto, Kenji Takano, Kenji Ilda, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
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Publication number: 20060112544Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.Type: ApplicationFiled: November 4, 2005Publication date: June 1, 2006Applicant: FUJITSU LIMITEDInventors: Takashi Shuto, Kenji Takano, Kenji IIda, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
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Patent number: 6959125Abstract: It is an object of the present invention to enhance laser beam transmitting efficiency by accurately controlling an interval between a light emitting (light receiving) element (20) and an optical wave-guide substrate (1) without causing any fluctuation in the interval in a mounting structure of the light transmitting element in which the light emitting (light receiving) element (20) is mounted on the optical wave-guide substrate (1). When the light emitting (light receiving) element is joined to the sub-mount chip (4) and when the sub-mount chip (4) is joined to the optical wave-guide while the element is being directed to the substrate side, the sub-mount chip and the optical wave-guide substrate are joined to each other by the solder bump (6). A post (5) is arranged for regulating an interval between the light emitting (light receiving) element and the optical wave-guide substrate.Type: GrantFiled: January 14, 2003Date of Patent: October 25, 2005Assignee: Fujitsu LimitedInventors: Takashi Kanda, Kiyotaka Seyama, Kaoru Sugimoto, Souichi Obata, Yasutomo Maehara
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Patent number: 6693362Abstract: A multichip module is provided. The multichip module comprises a rigid substrate including a core material and having an opening, a thin film fixed on an upper surface of the rigid substrate so as to be electrically connected to the rigid substrate and to close the opening, a first chip mounted on the upper surface of the thin film, and a second chip mounted on the under surface of the thin film so as to be located in the opening of the rigid substrate. The rigid substrate and the thin film form a wiring substrate having a composite structure.Type: GrantFiled: November 20, 2001Date of Patent: February 17, 2004Assignee: Fujitsu LimitedInventors: Kiyotaka Seyama, Hiroshi Yamada, Haruhiko Yamamoto
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Publication number: 20030228084Abstract: It is an object of the present invention to enhance laser beam transmitting efficiency by accurately controlling an interval between a light emitting (light receiving) element (20) and an optical wave-guide substrate (1) without causing any fluctuation in the interval in a mounting structure of the light transmitting element in which the light emitting (light receiving) element (20) is mounted on the optical wave-guide substrate (1). When the light emitting (light receiving) element is joined to the sub-mount chip (4) and when the sub-mount chip (4) is joined to the optical wave-guide while the element is being directed to the substrate side, the sub-mount chip and the optical waveguide substrate are joined to each other by the solder bump (6). A post (5) is arranged for regulating an interval between the light emitting (light receiving) element and the optical wave-guide substrate.Type: ApplicationFiled: January 14, 2003Publication date: December 11, 2003Applicant: FUJITSU LIMITEDInventors: Takashi Kanda, Kiyotaka Seyama, Kaoru Sugimoto, Souichi Obata, Yasutomo Maehara
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Publication number: 20020149098Abstract: A multichip module is provided. The multichip module comprises a rigid substrate including a core material and having an opening, a thin film fixed on an upper surface of the rigid substrate so as to be electrically connected to the rigid substrate and to close the opening, a first chip mounted on the upper surface of the thin film, and a second chip mounted on the under surface of the thin film so as to be located in the opening of the rigid substrate. The rigid substrate and the thin film form a wiring substrate having a composite structure.Type: ApplicationFiled: November 20, 2001Publication date: October 17, 2002Applicant: FUJITSU LIMITEDInventors: Kiyotaka Seyama, Hiroshi Yamada, Haruhiko Yamamoto
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Patent number: 6057168Abstract: A method for forming bumps including the steps of forming bumps on a dummy wafer. The dummy wafer is diced into dummy chips and the bumps formed on the dummy chips are inspected. Thus only good bumps are transferred to a real chip on which circuit patterns are formed.Type: GrantFiled: January 27, 1999Date of Patent: May 2, 2000Assignee: Fujitsu LimitedInventors: Kiyotaka Seyama, Hideki Ota, Yasuhiro Usui, Kazuaki Satoh
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Patent number: 5894882Abstract: A heat sink structure of a module substrate includes a plurality of stripe-like bottom regions extending in a longitudinal direction and repeated in a lateral direction with a predetermined pitch, a plurality of stripe-like top regions extending in said longitudinal direction and repeated in the lateral direction with said predetermined pitch, such that the stripe-like bottom regions and the stripe-like top regions are repeated alternately in the lateral direction, wherein the stripe-like top regions and the stripe-like bottom regions have respective lateral edges that are connected with each other by cooling fins.Type: GrantFiled: May 17, 1996Date of Patent: April 20, 1999Assignee: Fujitsu LimitedInventors: Shunichi Kikuchi, Minoru Hirano, Kiyotaka Seyama, Hideaki Yoshimura, Takashi Kanda, Hitoshi Nori
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Patent number: 5862038Abstract: A cooling device for a mounting module in which heat generated from a predetermined number of circuit elements mounted on the mounting module is dissipated by a cooling arrangement. The cooling device is comprised of at least one conduction element which thermally connects the circuit element with the cooling arrangement, the conduction element includes a predetermined number of first conductive members which is placed in a respective hole formed in the conduction arrangement and is movably supported by a first conductive material filled between the side surface of the first conductive member and the surface of the conduction element so as to complete a thermal flow from the circuit element to the cooling arrangement.Type: GrantFiled: March 20, 1997Date of Patent: January 19, 1999Assignee: Fujitsu LimitedInventors: Masahiro Suzuki, Junichi Ishimine, Hisashi Kawashima, Keizo Takemura, Kiyotaka Seyama
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Patent number: 5608192Abstract: A multilayer thin-film wiring board formed by laminating at least three wiring layers including first, second, and third wiring layers together with a dielectric layer. The first wiring layer includes a first pattern having a plurality of first windows arranged with the same pitch both in a lateral direction and in a longitudinal direction of the wiring board, and a plurality of first island patterns each located at a substantially central portion of each first window. Similarly, the second wiring layer includes a second pattern having a plurality of second windows, and a plurality of second island patterns each located at a substantially central portion of each second window. The second windows are shifted from the first windows by half the pitch both in the lateral direction and in the longitudinal direction. The third wiring layer includes first and second via pads formed on a surface of the wiring board.Type: GrantFiled: July 26, 1995Date of Patent: March 4, 1997Assignee: Fujitsu LimitedInventors: Kiyokazu Moriizumi, Kiyotaka Seyama
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Patent number: 5586006Abstract: A multi-chip module includes a base board, a thin-film multi-layer circuit board which is provided on a first surface of the base board and has a multi-layer structure in which insulating layers and wiring conductors are stacked, circuit elements mounted on a main surface of the thin-film multi-layer circuit board, and terminals which are attached to the main surface of the thin-film multi-layer circuit board and electrically connect the wiring conductors to circuits formed on a wiring board on which the multi-chip module is mounted.Type: GrantFiled: December 15, 1995Date of Patent: December 17, 1996Assignee: Fujitsu LimitedInventors: Kiyotaka Seyama, Shunichi Kikuchi, Makoto Sumiyoshi, Naoki Yasuda, Minoru Hirano, Hitoshi Nori
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Patent number: 5432675Abstract: A multi-chip module (MCM) having semiconductor chips on a top surface of multi-layered interconnection circuits formed on a planar surface of a substrate including: (a) multi-layered interconnection circuits comprising alternatively laminated interconnection layers with insulating layers, and thermal contacts, each of the thermal contacts comprising successively laminated interconnection layers on a bottom and on side-walls of a vertical hole penetrating a plurality of the insulating layers, and a thermal conductor filling the vertical hole on the successively laminated interconnection layers, and (b) a plurality of the semiconductor chips attached to the thermal conductor.Type: GrantFiled: November 15, 1993Date of Patent: July 11, 1995Assignee: Fujitsu LimitedInventors: Haruo Sorimachi, Kiyotaka Seyama, Makoto Sumiyoshi, Kazuaki Satoh
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Patent number: 5181317Abstract: A method of making an engineering change to a printed wiring board changes connection for a terminal of an electronic component which is mounted on the printed wiring board through a terminal pad. The terminal is electrically connected to a destination through the terminal pad and wiring within the printed wiring board. The present invention places an insulator, including an insulating material and a conductive layer formed thereon, between the terminal and the terminal pad. The electronic component is mounted on the printed wiring board and the terminal is electrically connected to the conductive layer. A discrete wire is placed between the conductive layer and the destination.Type: GrantFiled: September 27, 1991Date of Patent: January 26, 1993Assignee: Fujitsu LimitedInventors: Mikio Nishihara, Teruo Murase, Kiyotaka Seyama, Kiyoshi Kuwabara, Osamu Ohshima
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Patent number: 5166867Abstract: A massive bus bar for supplying a determined power voltage to a circuit component mounted on a rigid circuit board having a conductor layer connecting the component to a bus bar connecting pad formed on the surface of the board. Plurality of first notches extend through a main surface of the bus bar from a common longitudinal edge, perpendicularly to the longitudinal axis of the bus bar and throughout the full longitudinal extent of the bus bar, and define a plurality of posts which are secured at their bottom surfaces to the conductive pads on the circuit board surface. The first notches facilitate flexing of the bus bar and reduce stresses otherwise produced due to the rigid connection of the bus bar to the circuit board, while not significantly diminishing the current handling capability of the bus bar.Type: GrantFiled: March 17, 1987Date of Patent: November 24, 1992Assignee: Fujitsu LimitedInventors: Kiyotaka Seyama, Seiichi Saito, Chikayuki Kumagai, Toshinari Hayashi
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Patent number: 4949219Abstract: A sealed module includes a cold plate having a passage through which a cooling medium flows, a plurality of bellows structures having first ends which communicate with the passage in the cold plate to form a thermal conduction type cooling system and a plated printed circuit having a substrate and a plurality of integrated circuit elements provided on a first surface the substrate. The integrated circuit elements are in contact with ends of the bellows structures. A metal fitting secured on the cold plate has a flange disposed beneath the other surface of the substrate to present a junction between the second surface of the substrate and the flange of the metal fitting. A polyimide layer is formed on the surface of the substrate and a conductor layer is formed on the polyimide layer. The polyimide layer and the conductor layer are approximately ring shaped at least at the peripheral portions of the substrate.Type: GrantFiled: May 24, 1989Date of Patent: August 14, 1990Assignee: Fujitsu LimitedInventors: Kiyokazu Moriizumi, Kyoichiro Kawano, Kiyotaka Seyama
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Patent number: 4912603Abstract: A high density printed wiring board, on which terminal pads are provided and high density semiconductor devices each having input and output terminals are mounted through the terminal pads, is provided with via pads which are internally connected with respective previously designated circuits of the board and are placed adjacent each terminal pad and are electrically connected with the corresponding terminal pad by a wiring pattern provided on the surface of the board. When the destination of the terminal pad is to be modified for connection with another circuit of the board, the wiring pattern is severed and electrical connection between the terminal pad and the other circuit is made using insulated new discrete wiring wired on the surface of the board.Type: GrantFiled: March 23, 1989Date of Patent: March 27, 1990Assignee: Fujitsu LimitedInventor: Kiyotaka Seyama