Kiyoyuki Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: At a time of band width compression, an input signal is separated into a horizontal high frequency component H and a horizontal low frequency component L by means of an LPF and an adder. The component H is subjected to in-frame averaging by an in-frame average circuit. The component L is delayed by one field by a field delay circuit which contains a component to provide smooth motion. The delayed output is added to the in-frame average output in one field by an adder. In the other field, a difference in the horizontal low frequency component between fields is attained by a field delay circuit and an adder. Accordingly, in one field a signal containing the component L and the component H subjected to in-frame averaging is attained. In the other field, a signal containing only the component L having gone through a process of obtaining the field-to-field difference is attained. At a time of band width reproduction, an input signal is output as it is in one field through two switch circuits.
Abstract: A wide aspect ratio screen color television system, such as a 16:9 aspect ratio screen television system, includes a signal generating circuit for generating the wide aspect ratio screen color television signal with a predetermined two-dimensional frequency band, a screen separating circuit for separating the color television signal into at least a first television signal relating to a relatively narrow aspect ratio portion and second television signal relating to an excess portion thereover, a circuit for eliminating a prescribed high frequency region of the two-dimensional frequency band of the first television signal, a signal suppressing circuit for suppressing the frequency band of the second television signal and a signal multiplexing circuit for multiplexing the suppressed second television signal onto the two-dimensional high frequency band region in place of the eliminated portion of the first television signal.
Abstract: A noninterlaced Y signal is separated into a horizontal high frequency component H and a horizontal low frequency component L by a LPF and an adder circuit at a time of interlace conversion. The component H is converted to an interlaced signal by a field repeating process comprising an interfield averaging process by an interfield averaging circuit, a field thinning out process by a field thinning out circuit and a delay process by an interlace conversion circuit. On the other hand, the component L is converted to an interlaced signal by a line thinning out process by an interlace conversion circuit. At a time of noninterlace conversion, the interlaced Y signal is separated into the components H and L by an LPF and an adder circuit.
Abstract: A color subcarrier reproducing circuit reproduces a color subcarrier on the basis of a color burst signal in a color television signal in which phase reference data synchronized with the color burst signal is inserted in a predetermined position in a vertical blanking period, and provides a first clock signal whose frequency is equal to the frequency of the color subcarrier and a second clock signal whose frequency is four times the subcarrier frequency. The second clock signal is frequency-divided by first and second frequency dividers to produce a reproduced horizontal sync signal, and frequency-divided by first and third frequency dividers to produce a reproduced vertical sync signal. A phase reference data reproducing circuit reproduces the phase reference data from the color television signal using the first clock signal as a sampling signal.
Abstract: A sample rate conversion circuit converts first digital data processed by a first clock signal having a first frequency into digital data processed by a second clock signal having a second frequency. A ring oscillator has a predetermined number of voltage-controlled gate delay elements connected to each other in the form of a loop so as to output polyphase delay clock signals and a predetermined self-excited oscillation signal. A phase-locking circuit applies a control voltage corresponding to a phase difference between the first clock signal and the self-excited oscillation signal to each of the voltage-controlled gate delay elements so as to phase-lock the first clock signal with the self-excited oscillation signal output from the ring oscillator. A latch circuit latches the polyphase delay clock signals output from the ring oscillator in accordance with the second clock signal.
Abstract: A data bandwidth compressor receives an input digital video signal which includes first and second signal components, compresses the data bandwidth of the signal, and outputs a resultant signal. A line difference detector includes a line memory for storing the output signal from the data bandwidth compressor and detects a difference signal between adjacent lines. A frame difference detector includes a frame memory for storing the output signal from the data bandwidth compressor and detects a difference signal between adjacent frames. A motion detector receives the output signal from the data bandwidth compressor and detects an image motion signal included in the output signal. A first separator separates and outputs the first signal component by changing the mixing ratio of the line and frame difference signals, in accordance with the image motion signal.
Abstract: A first digital data processing system outputs digital data obtained by sampling, in response to a clock signal of a first frequency, original data having a characteristic enabling interpolation thereof. A second digital data processing system obtaines output data by sampling input data in response to a clock signal of a second frequency. A sample rate conversion circuit receives the digital data from the first digital data processing system, converts the sample rate thereof into a sample rate suitable for the second digital data processing system, and supplies the sample rate as the input data to the second digital data processing system.
Abstract: A frame memory stores one-frame data of an input digital video signal and outputs the stored data as a one-frame delayed digital video signal. A first motion data generator receives the input digital video signal and the one-frame delayed digital signal from the frame memory and generates first motion data in accordance with the difference between these two signals. A data compander receives the one-frame delayed digital video signal from the frame memory, compands the data amount of the one-frame delayed digital video signal, and oututs the resultant signal. A sub-frame memory stores the output signa from the data compander and outputs the stored data as a two-frame delayed signal. A data expander receives the two-frame delayed output signal from the sub-frame memory, expands the two-frame delayed output signal to the original data amount, and outputs the resultant signal.