Patents by Inventor Kiyoyuki Morita
Kiyoyuki Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9147722Abstract: A thin-film semiconductor substrate includes a top-gate first TFT, a top-gate second TFT, and a data line (source line), in which the first TFT has a first semiconductor layer, a first gate insulating film, a first gate electrode, a first source electrode, a first drain electrode, and a first protection layer, the second TFT has a second semiconductor layer, a second gate insulating film, a second gate electrode, a second source electrode, a second drain electrode, and a second protection layer, the data line is connected to the first source electrode, the first drain electrode is an extension of the second gate electrode, and the second gate electrode is thinner than the data line.Type: GrantFiled: November 14, 2014Date of Patent: September 29, 2015Assignee: PANASONIC CORPORATIONInventors: Arinobu Kanegae, Kiyoyuki Morita
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Publication number: 20150069391Abstract: A thin-film semiconductor substrate includes a top-gate first TFT, a top-gate second TFT, and a data line (source line), in which the first TFT has a first semiconductor layer, a first gate insulating film, a first gate electrode, a first source electrode, a first drain electrode, and a first protection layer, the second TFT has a second semiconductor layer, a second gate insulating film, a second gate electrode, a second source electrode, a second drain electrode, and a second protection layer, the data line is connected to the first source electrode, the first drain electrode is an extension of the second gate electrode, and the second gate electrode is thinner than the data line.Type: ApplicationFiled: November 14, 2014Publication date: March 12, 2015Applicant: PANASONIC CORPORATIONInventors: Arinobu KANEGAE, Kiyoyuki MORITA
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Publication number: 20110001193Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.Type: ApplicationFiled: September 15, 2010Publication date: January 6, 2011Applicant: PANASONIC CORPORATIONInventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
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Patent number: 7821138Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.Type: GrantFiled: March 17, 2009Date of Patent: October 26, 2010Assignee: Panasonic CorporationInventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
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Publication number: 20090200582Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.Type: ApplicationFiled: March 17, 2009Publication date: August 13, 2009Applicant: PANASONIC CORPORATIONInventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
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Patent number: 7507297Abstract: A cleaning effect is improved by cleaning a component that has a recess structure by using a cleaning medium of a liquefied gas or a supercritical fluid. By the cleaning method of removing adhering substances adhering to at least the surface of the recess structure of the component that has the recess structure, cleaning is carried out by using the supercritical gas or the liquefied gas so that the cleaning medium spreads over the surface of the recess structure.Type: GrantFiled: May 12, 2003Date of Patent: March 24, 2009Assignee: Panasonic CorporationInventors: Yousuke Irie, Kiyoyuki Morita, Masaaki Suzuki, Akihisa Adachi, Masahiko Hashimoto
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Patent number: 7493353Abstract: A stochastic processor of the present invention includes a fluctuation generator configured to output an analog quantity having a fluctuation, a fluctuation difference calculation means configured to output fluctuation difference data with an output of the fluctuation generator added to analog difference between two data, a thresholding unit configured to perform thresholding on an output of the fluctuation difference calculation means to thereby generate a pulse, and a pulse detection means configured to detect the pulse output from the thresholding unit.Type: GrantFiled: February 20, 2004Date of Patent: February 17, 2009Assignee: Panasonic CorporationInventors: Michihito Ueda, Kiyoyuki Morita
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Patent number: 7394090Abstract: A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34). This non-volatile memory achieves high integration at low cost.Type: GrantFiled: May 14, 2007Date of Patent: July 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoyuki Morita, Noboru Yamada, Akihito Miyamoto, Takashi Ohtsuka, Hideyuki Tanaka
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Patent number: 7291857Abstract: A non-volatile memory (1) which comprises an insulating substrate (11) having a plurality of first electrodes (15) extending therethrough from a front surface of the substrate to a rear surface thereof, a second electrode (12) formed on one surface side of the substrate (11), and a recording layer (14) held between the first electrodes (15) and the second electrode (12) and variable in resistance value by electric pulses applied across the first electrodes (15) and the second electrode (12), the plurality of first electrodes (15) being electrically connected to the recording layer (14) in a region constituting a single memory cell (MC). The non-volatile memory (1) can be reduced in power consumption and has great freedom of design and high reliability.Type: GrantFiled: October 19, 2004Date of Patent: November 6, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideyuki Tanaka, Takashi Ohtsuka, Kiyoyuki Morita, Kiyoshi Morimoto
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Publication number: 20070210362Abstract: A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34). This non-volatile memory achieves high integration at low cost.Type: ApplicationFiled: May 14, 2007Publication date: September 13, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoyuki Morita, Noboru Yamada, Akihito Miyamoto, Takashi Ohtsuka, Hideyuki Tanaka
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Patent number: 7232703Abstract: A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34). This non-volatile memory achieves high integration at low cost.Type: GrantFiled: November 4, 2004Date of Patent: June 19, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoyuki Morita, Noboru Yamada, Akihito Miyamoto, Takashi Ohtsuka, Hideyuki Tanaka
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Patent number: 7220482Abstract: The present invention provides aligned fine particles that are aligned on a substrate. An organic coating film is bonded to surfaces of the fine particles is formed on the surfaces of the fine particles. An organic coating film bonded to a surface of the substrate is formed on the surface of the substrate. The organic coating film on the surfaces of the fine particles is bonded to the organic coating film on the surface of the substrate, whereby the fine particles are immobilized and aligned on the substrate. Thus, it is possible to align the fine particles of a nanometer scale in a specific direction. When fine magnetic particles are used, a magnetic recording medium for high recording density can be obtained, and a high-density magnetic recording/reproducing apparatus can be provided.Type: GrantFiled: January 22, 2002Date of Patent: May 22, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Norishisa Mino, Yasuhiro Kawawake, Kiyoyuki Morita, Shigeo Yoshii, Mutuaki Murakami, Osamu Kusumoto
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Publication number: 20060131662Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.Type: ApplicationFiled: October 26, 2005Publication date: June 22, 2006Inventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
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Patent number: 7053693Abstract: A voltage generating circuit comprising a capacitor (4), a ferroelectric capacitor (6) serially connected to the capacitor (4), an output terminal (11), a capacitor (10) which grounds the output terminal (11), a supply voltage supplying terminal (13), a switch (1) which connects the supply voltage supplying terminal (13) and the connecting node (N1) of the two capacitors (4, 6), and a switch (9) which connects the connecting node (N1) and output terminal (11); wherein during a first period, with the two switches (1) and (9) placed in the OFF state, a terminal (3) is grounded and a terminal (7) is provided with a supply voltage; wherein during a second period, the terminal (3) is provided with the supply voltage and the switch (9) is placed in the ON state; wherein during a third period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is grounded; wherein during a fourth period, the terminal (7) is provided with the supply voltage; and wherein thereafteType: GrantFiled: January 28, 2004Date of Patent: May 30, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Toyoda, Michihito Ueda, Kiyoshi Morimoto, Kiyoyuki Morita
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Publication number: 20060076558Abstract: An object of the present invention is to prevent a junction leakage current generation across a pn junction formed under a silicide layer, even when a direct probing to an electrode formed of the silicide layer is performed.Type: ApplicationFiled: September 2, 2005Publication date: April 13, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTDInventors: Kiyoyuki Morita, Hiroyuki Kamada, Keita Uchiyama
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Patent number: 7022530Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.Type: GrantFiled: April 3, 2002Date of Patent: April 4, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoyuki Morita, Shoji Miyake, Michihito Ueda, Takashi Ohtsuka, Takashi Nishikawa
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Patent number: 6949780Abstract: In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistor 54 is connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistor 56 is the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.Type: GrantFiled: May 18, 2004Date of Patent: September 27, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Michihito Ueda, Kenji Toyoda, Kiyoyuki Morita, Takashi Ohtsuka
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Publication number: 20050199263Abstract: A cleaning effect is improved by cleaning a component that has a recess structure by using a cleaning medium of a liquefied gas or a supercritical fluid. By the cleaning method of removing adhering substances adhering to at least the surface of the recess structure of the component that has the recess structure, cleaning is carried out by using the supercritical gas or the liquefied gas so that the cleaning medium spreads over the surface of the recess structure.Type: ApplicationFiled: May 12, 2003Publication date: September 15, 2005Inventors: Yousuke Irie, Kiyoyuki Morita, Masaaki Suzuki, Akihisa Adachi, Masahiko Hashimoto
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Patent number: 6940740Abstract: A semiconductor device includes: a control-voltage supply unit 110; an MOS transistor including a gate electrode 109 and drain and source regions 103a and 103b; a dielectric capacitor 104; and a resistor 106. The dielectric capacitor 104 and the resistor 106 are disposed in parallel and interposed between the gate electrode 109 and the control-voltage supply unit 110. With this structure, a charge is accumulated in each of an intermediate electrode of the dielectric capacitor 104 and the gate electrode 109 upon the application of a voltage, thereby varying a threshold value of the MOS transistor. In this manner, the history of input signals can be stored as a variation in a drain current in the MOS transistor, thus allowing multilevel information to be held.Type: GrantFiled: May 5, 2003Date of Patent: September 6, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Michihito Ueda, Takashi Ohtsuka, Kiyoyuki Morita
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Patent number: RE48032Abstract: A thin-film semiconductor substrate includes a top-gate first TFT, a top-gate second TFT, and a data line (source line), in which the first TFT has a first semiconductor layer, a first gate insulating film, a first gate electrode, a first source electrode, a first drain electrode, and a first protection layer, the second TFT has a second semiconductor layer, a second gate insulating film, a second gate electrode, a second source electrode, a second drain electrode, and a second protection layer, the data line is connected to the first source electrode, the first drain electrode is an extension of the second gate electrode, and the second gate electrode is thinner than the data line.Type: GrantFiled: September 28, 2017Date of Patent: June 2, 2020Assignee: PANASONIC CORPORATIONInventors: Arinobu Kanegae, Kiyoyuki Morita