Abstract: A mechanically stable main body having a cutout, into which an ESD protection element is at least partly embedded and mechanically fixed by means of a connection means. Electrical terminals of the protection element are connected to terminal pads on the top side of the main body by way of a structured metallic layer bearing on main body and protection element.

Abstract: Doped, low-temperature co-fired ceramic (LTCC) insulating substrates and related wiring boards and methods of manufacture are disclosed. The doped, LTCC insulating substrate is formed from a baked (e.g., sintered) glass-ceramic aggregate material formed from a glass material, a ceramic filler material, and a composite oxide. The crystallized glass-ceramic aggregate is then doped with Iron and/or Manganese before baking. Iron or Manganese can further reduce dielectric loss and the loss tangent of the LTCC insulating substrate formed from that glass material. The glass material becomes crystallized due to an oxide crystal phase being deposited on the glass material during baking, which reduces the dielectric losses. This may be important for the application use as wiring boards for high radio-frequency (RF) electrical circuits where low dielectric loss and loss tangent is desired to achieve a desired signal transmission delay performance.

Abstract: Doped, low-temperature co-fired ceramic (LTCC) insulating substrates and related wiring boards and methods of manufacture are disclosed. The doped, LTCC insulating substrate is formed from a baked (e.g., sintered) glass-ceramic aggregate material formed from a glass material, a ceramic filler material, and a composite oxide. The crystallized glass-ceramic aggregate is then doped with Iron and/or Manganese before baking. Iron or Manganese can further reduce dielectric loss and the loss tangent of the LTCC insulating substrate formed from that glass material. The glass material becomes crystallized due to an oxide crystal phase being deposited on the glass material during baking, which reduces the dielectric losses. This may be important for the application use as wiring boards for high radio-frequency (RF) electrical circuits where low dielectric loss and loss tangent is desired to achieve a desired signal transmission delay performance.

Abstract: A mechanically stable main body having a cutout, into which an ESD protection element is at least partly embedded and mechanically fixed by means of a connection means. Electrical terminals of the protection element are connected to terminal pads on the top side of the main body by way of a structured metallic layer bearing on main body and protection element.

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.

Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.

Abstract: A light-emitting diode device has a first carrier and at least one light-emitting diode chip, which is arranged on the first carrier. The first carrier has at least one first and one second carrier part, wherein the light-emitting diode chip rests only on the first carrier part. Furthermore, the first and second carrier parts each have a thermal conductivity. The thermal conductivity of the first carrier part is at least 1.5 times the thermal conductivity of the second carrier part. The first carrier part is surrounded laterally by the second carrier part.

Abstract: A light-emitting diode device has a first carrier and at least one light-emitting diode chip, which is arranged on the first carrier. The first carrier has at least one first and one second carrier part, wherein the light-emitting diode chip rests only on the first carrier part. Furthermore, the first and second carrier parts each have a thermal conductivity. The thermal conductivity of the first carrier part is at least 1.5 times the thermal conductivity of the second carrier part. The first carrier part is surrounded laterally by the second carrier part.

Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip, arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.

Abstract: A ceramic substrate includes a stack of layers that contain a ceramic material and that are sintered together. One layer, such as a top layer in the stack, has a higher proportion of a sintering agent than an adjacent layer. A metal paste may be applied to a top layer of the stack.

Abstract: A process for producing a ceramic substrate includes preparing a base body using a stack of layers that contain an unsintered ceramic material and a sintering agent, and sintering the stack of layers. At least one of the layers contains an increased proportion of sintering agent relative to an adjacent layer.

Abstract: A process for producing a ceramic substrate includes preparing a base body using a stack of layers that contain an unsintered ceramic material and a sintering agent, and sintering the stack of layers. At least one of the layers contains an increased proportion of sintering agent relative to an adjacent layer.

Abstract: Reduction-stable COG ceramic compounds having a high dielectric constant, particularly for multi-layer capacitors or LC filters with Cu electrodes, on the basis of the material system BaO—Nd2O3—Sm2O3—TiO2 in the region of the phase formation of rhombic bronzes with additives of a glass frit from the systems: (A) ZnO—B2O3—SiO2, (B) K2O—Na2O—BaO—Al2O3—ZrO2—ZnO—SiO2—B2O3 or (C) Li2O—BaO—B2O—SiO2, have the general formula BaII6−x(SmyNd1−y)8+2x/3Ti18O54+p wt. % glass frit with 1<x<2, 0.5<y<1.0 and 3<p<10.

Abstract: In a passive network, such as a CC array in the form of a chip, internal conductors of a number of capacitors are led out at a longitudinal side surface of a chip wafer as terminals therefor. Common frame electrodes of the number of capacitors are, in contrast, led out at both frontal side surfaces of the chip wafer.