Abstract: An integrated circuit including a resistive memory element is described. The resistive memory element includes a first solid electrolyte layer including a metal doped glass material, the glass material being at least partially amorphous, and a second solid electrolyte layer including the metal doped glass material. The resistive memory element also includes a middle layer disposed between the first and second solid electrolyte layers, the middle layer including a carbide composition.

Abstract: Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a plurality of the source/drain regions and the bitlines and formed of a material having a resistance that is switched by an applied voltage. Source lines are arranged parallel to the wordline stacks so that they connect further pluralities of the source/drain regions.

Abstract: A resistive memory element for reversibly switching between a high-resistance OFF state and a low-resistance ON state includes a reactive electrode, an inert electrode and a solid electrolyte arranged between the two electrodes. The resistive memory element further includes a nanomask structure arranged in the solid electrolyte, in particular at the inert electrode, where the nanomask structure is provided with openings through which the solid electrolyte makes contact with the inert electrode.

Abstract: One embodiment provides a non-volatile semiconductor memory with CBRAM memory cells at which there exists, between the Ag-doped GeSe layer and the Ag top electrode, a chemically inert barrier layer improving the switching properties of the CBRAM memory cell. The active matrix material layer of the memory cell includes a GeSe/Ge:H double layer with a vitreous GeSe layer and an amorphous Ge:H layer. The amorphous Ge:H layer is positioned between the GeSe layer and the second electrode. Thus, the forming of AgSe conglomerates in the Ag doping and/or electrode layer is inhibited, so that precipitations are prevented and a homogeneous deposition of the silver doping layer is enabled. By means of the GeSe/Ge:H double layer system, the resistive non-volatile storage effect of the CBRAM memory cell is, on the one hand, preserved and, on the other hand, the chemical stability of the top electrode positioned thereabove is ensured by means of the thin Ge:H layer.

Abstract: A non-volatile, resistively switching memory cell includes a first electrode, a second electrode and a solid electrolyte, which is arranged such that it makes contact between the electrodes, and is composed of an amorphous or partially amorphous, non-oxidic matrix and a metal which is distributed in the amorphous or partially amorphous, non-oxidic matrix and whose cations migrate to the cathode in the amorphous or partially amorphous, non-oxidic matrix under the influence of an electrical voltage, wherein the solid electrolyte contains one or more further metallic materials for stabilization of the amorphous state of the matrix.

Abstract: The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode and a second electrode with an active material positioned therebetween. The active material is adapted to be placed in a more or less electroconductive state by means of electrochemical switching processes. A CBRAM memory cell manufactured pursuant to the method according to the invention has, due to the improved conditioning, more reliable and more distinctly evaluable electrical switching properties. Moreover, no more forming step is necessary with the method according to the present invention.

Abstract: In a method for fabricating a nonvolatile memory element a substrate is provided, a nanomask structure is fabricated on the substrate and a self-assembled monolayer of an organic memory molecule is grown on the substrate on a region not covered by the nanomask structure. A surface of the substrate is patterned by means of an electrode beam in order to form regions with organic memory molecules and regions without organic memory molecules and a top contact is applied to the monolayer formed from the organic memory molecules and the nanomask.

Abstract: A method for fabricating a resistively switching memory cell is provided. The method includes the following steps: depositing a first electrode, applying a layer of a chalcogenide compound to the first electrode, applying a layer of silver or copper, and operating a noble gas plasma in a back-sputtering mode in order to effect silver or copper diffusion into the layer of the chalcogenide compound. Optionally, and if appropriate, further layers for the second electrode are then deposited.

Abstract: A nonvolatile memory cell is described, including a carbon layer system that includes an sp2-rich amorphous carbon layer and an sp3-rich amorphous carbon layer, wherein information is stored in the nonvolatile memory cell by reversibly forming an sp2-rich filament in the sp3-rich amorphous carbon layer.

Abstract: An integrated circuit is described, including a memory element including a first carbon layer rich in a first carbon material and a second carbon layer rich in a second carbon material. The memory element stores information by reversibly forming a conductive channel in the second carbon layer, wherein the conductive channel includes the first carbon material.

Abstract: A semiconductor memory cell, a method for fabricating it and a semiconductor memory device. A phase change material region of a storage element of the semiconductor memory cell has been or is formed as a lining region of a wall region of a contact recess which passes all the way through an insulation region between a first electrode device and a second electrode device. Furthermore, the space or region of the contact recess which is not taken up by the material region of the storage element has been or is made substantially electrically insulating.

Abstract: An information storage element has a carbon storage material including hexagonally bonded carbon and tetrahedrally bonded carbon. The information is formed by a changeable ratio of hexagonally bonded carbon and tetrahedrally bonded carbon.

Abstract: The object of providing a non-volatile semiconductor memory that stands out by good scalability and a high retention time as well as ensures low switching voltages at low switching times and achieves a great number of switching cycles at good temperature stability is solved by the present invention with a semiconductor memory whose memory cells comprise at least one silicon matrix material layer with open or disturbed nanocrystalline or amorphous network structures and structural voids which has a resistively switching property between two stable states, utilizing the ion drift in the silicon matrix material layer. The memory concept suggested in the present invention thus offers an alternative to the flash and DRAM memory concepts since it is not based on the storing of charges, but on the difference of the electric resistance between two stable states that are caused by the mobility of ions in the amorphous silicon matrix material with an externally applied electric field.

Abstract: The present invention relates to a reprogrammable non-volatile memory cell which comprises a selection transistor and a data storage element. The invention further relates to a method of fabricating such a memory cell, as well as to a memory cell array comprising a number of such memory cells.

Abstract: A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second conduction type provided in the semiconductor substrate, a channel region located between the first and second doping regions, a multilayer gate dielectric which is arranged adjacent to the channel region and has a charge trapping memory layer, and a gate terminal provided above the gate dielectric. The charge trapping memory layer includes at least one sequence of adjacent layers, wherein the sequence of adjacent layers comprises an amorphous silicon carbide layer and an amorphous silicon nitride layer.

Abstract: A programmable resistive memory cell comprising a lower electrode, a programmable resistance layer, and an upper electrode, wherein the programmable resistance layer comprises a first transition metal oxide and a second transition metal oxide.

Abstract: A programmable resistive memory cell comprising a lower electrode, a programmable resistance layer, and an upper electrode, wherein a lower mask is arranged between the lower electrode and the programmable resistance layer and an upper mask is arranged between the programmable resistance layer and the upper electrode, and wherein the lower mask and the upper mask comprise current-inhibiting regions.

Abstract: Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a plurality of the source/drain regions and the bitlines and formed of a material having a resistance that is switched by an applied voltage. Source lines are arranged parallel to the wordline stacks so that they connect further pluralities of the source/drain regions.

Abstract: Method of fabricating an integrated electronic circuit with programmable resistance cells, which comprises providing a substrate; forming an inert electrode; forming a solid electrolyte on the inert electrode; forming an interlayer on the solid electrolyte, the interlayer comprising an active electrode material and nitrogen; and forming an active electrode on the interlayer, the active electrode comprising the active electrode material.

Abstract: An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material (4) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.