Patents by Inventor Klaus Pressel

Klaus Pressel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10217695
    Abstract: An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip comprising at least one chip pad in the second main surface region and a connector block comprising at least one first electrically conductive through connection and at least one second electrically conductive through connection extending with different cross-sectional areas between the first main surface region and the second main surface region and being arranged side-by-side with the semiconductor chip.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Klaus Pressel, Maciej Wojnowski
  • Publication number: 20170162476
    Abstract: An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip comprising at least one chip pad in the second main surface region and a connector block comprising at least one first electrically conductive through connection and at least one second electrically conductive through connection extending with different cross-sectional areas between the first main surface region and the second main surface region and being arranged side-by-side with the semiconductor chip.
    Type: Application
    Filed: December 2, 2016
    Publication date: June 8, 2017
    Inventors: Thorsten MEYER, Klaus Pressel, Maciej Wojnowski
  • Patent number: 9601475
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: March 21, 2017
    Assignee: Intel Deutschland GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Publication number: 20160163682
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Application
    Filed: February 11, 2016
    Publication date: June 9, 2016
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 9293423
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 22, 2016
    Assignee: Intel Deutschland GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 8952521
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
  • Publication number: 20140332937
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Application
    Filed: July 14, 2014
    Publication date: November 13, 2014
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 8779563
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: July 15, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Brandl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 8779583
    Abstract: A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Klaus Pressel, Gottfried Beer
  • Publication number: 20140110840
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Application
    Filed: January 8, 2013
    Publication date: April 24, 2014
    Applicant: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
  • Patent number: 8598709
    Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: December 3, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gottfried Beer, Christian Geissler, Thomas Ort, Klaus Pressel, Bernd Waidhas, Andreas Wolter
  • Publication number: 20130228904
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Application
    Filed: November 9, 2012
    Publication date: September 5, 2013
    Applicant: INTEL MOBILE COMMUNICATIONS GMBH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Brandl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 8415803
    Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: April 9, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gottfried Beer, Christian Geissler, Thomas Ort, Klaus Pressel, Bernd Waidhas, Andreas Wolter
  • Patent number: 8338936
    Abstract: A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: December 25, 2012
    Assignee: Infineon Technologies AG
    Inventors: Klaus Pressel, Gottfried Beer
  • Publication number: 20120319304
    Abstract: A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 20, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Klaus Pressel, Gottfried Beer
  • Publication number: 20120287583
    Abstract: An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip.
    Type: Application
    Filed: July 25, 2012
    Publication date: November 15, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Klaus Pressel, Gottfried Beer
  • Patent number: 8309454
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: November 13, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 8237259
    Abstract: An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip. The electronic assembly further includes a substrate embedding the package structure.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: August 7, 2012
    Assignee: Infineon Technologies AG
    Inventors: Klaus Pressel, Gottfried Beer
  • Publication number: 20120049375
    Abstract: A method and a system for routing electrical connections of a plurality of chips are disclosed. In one embodiment, a semiconductor device is provided comprising at least one semiconductor chip, at least one routing plane comprising at least one routing line, and at least one connecting line electrically coupled to the at least one routing line and at least one semiconductor chip.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 1, 2012
    Inventors: Thorsten MEYER, Gottfried BEER, Christian GEISSLER, Thomas ORT, Klaus PRESSEL, Bernd WAIDHAS, Andreas WOLTER
  • Patent number: 7910404
    Abstract: A method of manufacturing a stacked die module includes applying a plurality of stacked die structures to a carrier. Each stacked die structure includes a first semiconductor die applied to the carrier and a second semiconductor die stacked over the first semiconductor die. The second semiconductor die has a larger lateral surface area than the first semiconductor die. A dam is applied around each of the stacked die structures, thereby forming an enclosed cavity for each of the stacked die structures. The enclosed cavity for each stacked die structure surrounds the first semiconductor die of the stacked die structure.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: March 22, 2011
    Assignee: Infineon Technologies AG
    Inventors: Klaus Pressel, Gottfried Beer