Patents by Inventor Klaus Schimpf

Klaus Schimpf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8330223
    Abstract: A bipolar transistor has a collector having a base layer provided thereon and a shallow trench isolation structure formed therein. A base poly layer is provided on the shallow trench isolation structure. The shallow trench isolation structure defines a step such that a surface of the collector projects from the shallow trench isolation structure adjacent the collector.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Klaus Schimpf, Manfred Schiekofer, Carl David Willis, Michael Waitschull, Wolfgang Ploss
  • Publication number: 20110049517
    Abstract: A bipolar transistor has a collector having a base layer provided thereon and a shallow trench isolation structure formed therein. A base poly layer is provided on the shallow trench isolation structure. The shallow trench isolation structure defines a step such that a surface of the collector projects from the shallow trench isolation structure adjacent the collector.
    Type: Application
    Filed: September 2, 2010
    Publication date: March 3, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Klaus SCHIMPF, Manfred SCHIEKOFER, Carl David WILLIS, Michael WAITSCHULL, Wolfgang PLOSS
  • Patent number: 7772060
    Abstract: A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor. Growing of the epitaxial layer includes growing a first sublayer of silicon 28a, a first sublayer of silicon-germanium 28b onto the first sublayer of silicon, a second sublayer of silicon 28c onto the first sublayer of silicon-germanium, and a second sublayer of silicon-germanium 28d onto the second sublayer of silicon. Furthermore, an integrated BiCMOS circuit is provided, which includes an epitaxial layer 28 as described above.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: August 10, 2010
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Reiner Jumpertz, Klaus Schimpf
  • Patent number: 7436003
    Abstract: A vertical thyristor for ESD protection comprises an anode (10), a cathode (16), a first gate electrode (12) and a second gate electrode (14). The first (12) and second (14) gate electrodes are arranged between the anode (10) and the cathode (16), wherein the first gate electrode (12) is an epitaxial silicon layer (20) formed upon the anode (10) and the second gate electrode (14) is an epitaxial silicon-germanium layer (24) formed upon the first gate electrode (12). The method of fabricating such a vertical thyristor comprises the steps of depositing an epitaxial silicon layer (20) upon the anode (10) and depositing an epitaxial silicon-germanium layer (24) upon the epitaxial silicon layer (20), wherein the epitaxial silicon layer (20) forms the first gate electrode (12) and the epitaxial silicon-germanium layer (24) forms the second gate electrode (14) of the vertical thyristor.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: October 14, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Reiner Jumpertz, Klaus Schimpf
  • Publication number: 20080149982
    Abstract: A CMOS transistor comprises a substrate with a gate electrode arranged thereon between source and drain regions. A capacitor is provided on the gate electrode and a voltage applied to the gate electrode is dropped across a stack, including the gate electrode and the capacitor.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 26, 2008
    Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Reiner Jumpertz, Klaus Schimpf, Stefan Bogen
  • Publication number: 20070298561
    Abstract: A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor. Growing of the epitaxial layer includes growing a first sublayer of silicon 28a, a first sublayer of silicon-germanium 28b onto the first sublayer of silicon, a second sublayer of silicon 28c onto the first sublayer of silicon-germanium, and a second sublayer of silicon-germanium 28d onto the second sublayer of silicon. Furthermore, an integrated BiCMOS circuit is provided, which includes an epitaxial layer 28 as described above.
    Type: Application
    Filed: June 11, 2007
    Publication date: December 27, 2007
    Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Reiner Jumpertz, Klaus Schimpf
  • Publication number: 20060175629
    Abstract: A vertical thyristor for ESD protection comprises an anode (10), a cathode (16), a first gate electrode (12) and a second gate electrode (14). The first (12) and second (14) gate electrodes are arranged between the anode (10) and the cathode (16), wherein the first gate electrode (12) is an epitaxial silicon layer (20) formed upon the anode (10) and the second gate electrode (14) is an epitaxial silicon-germanium layer (24) formed upon the first gate electrode (12). The method of fabricating such a vertical thyristor comprises the steps of depositing an epitaxial silicon layer (20) upon the anode (10) and depositing an epitaxial silicon-germanium layer (24) upon the epitaxial silicon layer (20), wherein the epitaxial silicon layer (20) forms the first gate electrode (12) and the epitaxial silicon-germanium layer (24) forms the second gate electrode (14) of the vertical thyristor.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 10, 2006
    Inventors: Reiner Jumpertz, Klaus Schimpf
  • Publication number: 20020109206
    Abstract: A lateral PNP-type transistor, and a process for producing such lateral PNP-type transistor from a substrate are provided. In particular, a PNP-emitter and a PNP-collector. The PNP-collector is provided at a predetermined distance from the PNP emitter. The PNP-emitter is electrically insulated from the PNP-collector.
    Type: Application
    Filed: December 7, 2001
    Publication date: August 15, 2002
    Inventor: Klaus Schimpf