Patents by Inventor Kohei Sasaki

Kohei Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11469334
    Abstract: An object of the present invention is to provide a Schottky barrier diode less apt to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode includes a semiconductor substrate 20 made of gallium oxide, a drift layer 30 made of gallium oxide and provided on the semiconductor substrate 20, an anode electrode 40 brought into Schottky contact with the drift layer 30, and a cathode electrode 50 brought into ohmic contact with the semiconductor substrate 20. The drift layer 30 has an outer peripheral trench 10 that surrounds the anode electrode 40 in a plan view, and the outer peripheral trench 10 is filled with a semiconductor material 11 having a conductivity type opposite to that of the drift layer 30. An electric field is dispersed by the presence of the thus configured outer peripheral trench 10. This alleviates electric field concentration on the corner of the anode electrode 40, making it less apt to cause dielectric breakdown.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: October 11, 2022
    Assignees: TDK CORPORATION, TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.
    Inventors: Jun Arima, Minoru Fujita, Jun Hirabayashi, Kohei Sasaki
  • Patent number: 11453205
    Abstract: An interlayer film for laminated glass has enhanced sound insulating properties at 30° C., and includes first and second layers each containing a thermoplastic resin and a plasticizer. When an absolute value of a difference in cloud point using the thermoplastic resin and plasticizer in each of the first and second layers is Xa, and a content in parts by weight of the entire plasticizer in the interlayer film relative to 100 parts by weight of the entire thermoplastic resin in the interlayer film Z, the interlayer film satisfies the first constitution: “Xa?115 and Z??0.16Xa+59” and/or the second constitution: “the thermoplastic resin in the first layer is polyvinyl acetal resin, and when the acetylation degree on a mole percent basis of the polyvinyl acetal resin in the first layer is represented by Y, Y?2 and Z??0.16Xa?0.2Y+59”.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: September 27, 2022
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Nami Minakuchi, Tatsuya Iwamoto, Kohei Kani, Jun Sasaki, Yuuma Takeda
  • Patent number: 11456388
    Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer stacked on the first semiconductor layer, includes a Ga2O3-based single crystal, and includes a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench electrode that is buried in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes an insulating dry-etching-damaged layer with a thickness of not more than 0.8 ?m in a region including the inner surface of the trench.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 27, 2022
    Assignees: Tamura Corporation, Novel Crystal Technology, Inc., TDK Corporation
    Inventors: Kohei Sasaki, Minoru Fujita, Jun Hirabayashi, Jun Arima
  • Patent number: 11445609
    Abstract: There is provided a printed circuit board in which an amount of molten solder adhering over electrodes adjacent to each other is increased in flow soldering. The printed circuit board according to the present invention includes: a first insulating substrate (6) having a mounting hole (15) that penetrates through the first insulating substrate (6) from a first surface (6a) to a second surface (6b); a second insulating substrate (18) including a connection portion (23a) that penetrates through the mounting hole (15) from the first surface (6a) side and protrudes from the second surface (6b); first electrodes (7 and 9) that are provided on the second surface (6b) and are arranged at an edge of the mounting hole (15); and second electrodes (19 and 25) provided on the connection portion (23a). The first electrodes (7 and 9) and the second electrodes (19 and 25) are joined by solder.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: September 13, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshiko Fujima, Toshiki Asai, Yusuke Morimoto, Kohei Sato, Shunsuke Sasaki
  • Patent number: 11432403
    Abstract: A printed circuit board includes: a first insulating substrate having a mounting hole that penetrates through the first insulating substrate from a first surface to a second surface; a second insulating substrate including a connection portion; a first electrode provided on the second surface and disposed at an edge of the mounting hole; a second electrode provided on the connection portion and joined to the first electrode; and an electronic component provided on the second surface. A center of mass of the second insulating substrate is disposed on the first surface of the first insulating substrate. A center of mass of the electronic component is disposed on the second surface of the first insulating substrate. The electronic component has a weight equivalent to a weight of the second insulating substrate.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: August 30, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshiko Fujima, Toshiki Asai, Yusuke Morimoto, Kohei Sato, Shunsuke Sasaki
  • Patent number: 11355594
    Abstract: A diode includes an n-type semiconductor layer including an n-type Ga2O3-based single crystal, and a p-type semiconductor layer including a p-type semiconductor in which a volume of an amorphous portion is higher than a volume of a crystalline portion. The n-type semiconductor layer and the p-type semiconductor layer form a pn junction.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 7, 2022
    Assignees: Tamura Corporation, Novel Crystal Technology, Inc.
    Inventor: Kohei Sasaki
  • Patent number: 11264241
    Abstract: A semiconductor substrate includes a single crystal Ga2O3-based substrate and a polycrystalline substrate that are bonded to each other. A thickness of the single crystal Ga2O3-based substrate is smaller than a thickness of the polycrystalline substrate, and a fracture toughness value of the polycrystalline substrate is higher than a fracture toughness value of the single crystal Ga2O3-based substrate.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: March 1, 2022
    Assignees: TAMURA CORPORATION, SICOXS Corporation, National Institute of Information and Commnications Technology
    Inventors: Akito Kuramata, Shinya Watanabe, Kohei Sasaki, Kuniaki Yagi, Naoki Hatta, Masataka Higashiwaki, Keita Konishi
  • Publication number: 20210404086
    Abstract: As one embodiment, the present invention provides a method for growing a ?-Ga2O3-based single crystal film by using HYPE method. The method includes a step of exposing a Ga2O3-based substrate to a gallium chloride-based gas and an oxygen-including gas, and growing a ?-Ga2O3-based single crystal film on a principal surface of the Ga2O3-based substrate at a growth temperature of not lower than 900° C.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Applicants: TAMURA CORPORATION, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Ken GOTO, Kohei SASAKI, Akinori KOUKITU, Yoshinao KUMAGAI, Hisashi MURAKAMI
  • Publication number: 20210343879
    Abstract: An object of the present invention is to provide a Schottky barrier diode less liable to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode according to this disclosure includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, and a cathode electrode brought into ohmic contact with the semiconductor substrate. The drift layer has an outer peripheral trench surrounding the anode electrode in a plan view. The surface of the drift layer positioned between the anode electrode and the outer peripheral trench is covered with a semiconductor layer having a conductivity type opposite to that of the drift layer.
    Type: Application
    Filed: October 9, 2019
    Publication date: November 4, 2021
    Inventors: Jun ARIMA, Minoru FUJITA, Jun HIRABAYASHI, Kohei SASAKI
  • Publication number: 20210343880
    Abstract: An object of the present invention is to provide a Schottky barrier diode less liable to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode according to this disclosure includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode 40 brought into Schottky contact with the drift layer, a cathode electrode brought into ohmic contact with the semiconductor substrate, an insulating layer provided on the drift layer so as to surround the anode electrode in a plan view, and a semiconductor layer provided on a surface of a part of the drift layer that is positioned between the anode electrode and the insulating layer and on the insulating layer. The semiconductor layer has a conductivity type opposite to that of the drift layer.
    Type: Application
    Filed: October 9, 2019
    Publication date: November 4, 2021
    Inventors: Jun ARIMA, Minoru FUJITA, Jun HIRABAYASHI, Kohei SASAKI
  • Publication number: 20210238766
    Abstract: Provided is a Ga2O3-based single crystal substrate capable of achieving a high processing yield. A Ga2O3-based single crystal substrate having a crack density of less than 0.05 cracks/cm can be obtained that has as a principal surface thereof a surface rotated 10-150° from the (100) plane, when a rotation direction from the (100) plane to the (001) plane via the (101) plane is defined as positive, having the [010] axis as the rotation axis.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 5, 2021
    Applicant: TAMURA CORPORATION
    Inventor: Kohei SASAKI
  • Patent number: 11081598
    Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering an inner surface of the trench, and a trench MOS gate that is buried in the trench so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes a lower layer on a side of the first semiconductor layer and an upper layer on a side of the anode electrode having a higher donor concentration than the lower layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 3, 2021
    Assignees: TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Patent number: 11043602
    Abstract: Provided is a Schottky barrier diode which is configured from a Ga2O3-based semiconductor, and has a lower rising voltage than a conventional one. In one embodiment, the Schottky barrier diode 1 is provided which has: a semiconductor layer 10 configured from a Ga2O3-based single crystal; an anode electrode 11 which forms a Schottky junction with the semiconductor layer 10, and has a portion which contacts the semiconductor layer 10 and is composed of Fe or Cu; and a cathode electrode 12.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 22, 2021
    Assignees: Tamura Corporation, Novel Crystal Technology, Inc.
    Inventors: Kohei Sasaki, Daiki Wakimoto, Yuki Koishikawa, Quang Tu Thieu
  • Publication number: 20210167225
    Abstract: A Schottky barrier diode includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, and a cathode electrode brought into ohmic contact with the semiconductor substrate. The drift layer has a plurality of trenches formed in a position overlapping the anode electrode in a plan view. Among the plurality of trenches, a trench positioned at the end portion has a selectively increased width. Thus, the curvature radius of the bottom portion of the trench is increased, or an edge part constituted by the bottom portion as viewed in a cross section is divided into two parts. As a result, an electric field to be applied to the bottom portion of the trench positioned at the end portion is mitigated, making dielectric breakdown less likely to occur.
    Type: Application
    Filed: September 26, 2018
    Publication date: June 3, 2021
    Inventors: Jun ARIMA, Jun HIRABAYASHI, Minoru FUJITA, Kohei SASAKI
  • Publication number: 20210151611
    Abstract: A Schottky barrier diode includes a semiconductor layer including a Ga2O3-based single crystal, an anode electrode that forms a Schottky junction with the semiconductor layer and is configured so that a portion in contact with the semiconductor layer includes Mo or W, and a cathode electrode. A turn-on voltage thereof is not less than 0.3 V and not more than 0.5 V.
    Type: Application
    Filed: June 12, 2018
    Publication date: May 20, 2021
    Applicants: TAMURA CORPORATION, Novel Crystal Technology, Inc.
    Inventors: Kohei SASAKI, Daiki WAKIMOTO, Yuki KOISHIKAWA, Quang Tu THIEU
  • Patent number: 11011653
    Abstract: Provided is a Schottky barrier diode which is configured from a Ga2O3-based semiconductor, and has a lower rising voltage than a conventional one. In one embodiment, the Schottky barrier diode 1 is provided which has: a semiconductor layer 10 configured from a Ga2O3-based single crystal; an anode electrode 11 which forms a Schottky junction with the semiconductor layer 10, and has a portion which contacts the semiconductor layer 10 and is composed of Fe or Cu; and a cathode electrode 12.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: May 18, 2021
    Assignees: Tamura Corporation, Novel Crystal Technology, Inc.
    Inventors: Kohei Sasaki, Daiki Wakimoto, Yuki Koishikawa, Quang Tu Thieu
  • Publication number: 20210119062
    Abstract: An object of the present invention is to provide a Schottky barrier diode less apt to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode includes a semiconductor substrate 20 made of gallium oxide, a drift layer 30 made of gallium oxide and provided on the semiconductor substrate 20, an anode electrode 40 brought into Schottky contact with the drift layer 30, and a cathode electrode 50 brought into ohmic contact with the semiconductor substrate 20. The drift layer 30 has an outer peripheral trench 10 that surrounds the anode electrode 40 in a plan view, and the outer peripheral trench 10 is filled with a semiconductor material 11 having a conductivity type opposite to that of the drift layer 30. An electric field is dispersed by the presence of the thus configured outer peripheral trench 10. This alleviates electric field concentration on the corner of the anode electrode 40, making it less apt to cause dielectric breakdown.
    Type: Application
    Filed: March 11, 2019
    Publication date: April 22, 2021
    Inventors: Jun ARIMA, Minoru FUJITA, Jun HIRABAYASHI, Kohei SASAKI
  • Publication number: 20210020789
    Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer stacked on the first semiconductor layer, includes a Ga2O3-based single crystal, and includes a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench electrode that is buried in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes an insulating dry-etching-damaged layer with a thickness of not more than 0.8 ?m in a region including the inner surface of the trench.
    Type: Application
    Filed: February 25, 2019
    Publication date: January 21, 2021
    Applicants: TAMURA CORPORATION, Novel Crystal Technology, Inc., TDK Corporation
    Inventors: Kohei SASAKI, Minoru FUJITA, Jun HIRABAYASHI, Jun ARIMA
  • Patent number: 10861945
    Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a channel layer on the buffer layer, the channel layer including a ?-Ga2O3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a ?-Ga2O3-based single crystal including a donor impurity.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: December 8, 2020
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Kohei Sasaki, Ken Goto, Masataka Higashiwaki, Man Hoi Wong, Akinori Koukitu, Yoshinao Kumagai, Hisashi Murakami
  • Patent number: 10825935
    Abstract: A trench MOS-type Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer opposite to the second semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench MOS gate that is embedded in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: November 3, 2020
    Assignees: TAMURA CORPORATION, National Institute of Information and Communications Technology
    Inventors: Kohei Sasaki, Masataka Higashiwaki