Patents by Inventor Kohhei Kishi

Kohhei Kishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5026143
    Abstract: An active liquid crystal matrix display panel has a plurality of display-driving circuit elements arranged in a matrix on one of the cell substrates, the circuit elements being interconnected by bus-bars. The circuit elements are produced by a group exposure method. The bus-bars are formed wider at the group exposure boundaries so as to ensure continuity of the bus-bars.
    Type: Grant
    Filed: August 17, 1989
    Date of Patent: June 25, 1991
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hirohisa Tanaka, Kohhei Kishi, Kohzo Yano
  • Patent number: 4772099
    Abstract: A liquid crystal display device comprises a sandwich structure of support plates with a layer of liquid crystal filled therebetween. One support plate has an array of thin film transistors and thin film capacitors both formed thereon, while the other support plate has a counter electrode formed thereon. One of a pair of electrodes of each thin film capacitor on the one support plate is offset from the counter electrode at any area other than area where they form an effective capacitance element, the other the area where they form an effective capacitance element, the other capacitor electrodes serving as display electrodes.
    Type: Grant
    Filed: October 1, 1981
    Date of Patent: September 20, 1988
    Assignees: Sharp Kabushiki Kaisha, Japan Electronic Industry Development Association
    Inventors: Hiroaki Kato, Keisaku Nonomura, Kohhei Kishi, Tomio Wada
  • Patent number: 4746628
    Abstract: A thin film transistor (TFT) of a self-aligned structure, wherein a pair of a source electrode and a drain electrode are formed in alignment with a gate electrode and in contact with low resistance areas formed at both side portions of a semiconductor layer deposited on an insulating substrate. The low resistance areas are formed by the diffusion of metal atoms through heat-treatment.
    Type: Grant
    Filed: August 29, 1986
    Date of Patent: May 24, 1988
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Kohhei Kishi, Kohzo Yano
  • Patent number: 4684435
    Abstract: An improved process for manufacturing a thin film transistor uses two masks for etching and therefore one mask alignment. The technical effect of said process is to provide the thin film transistor with low cost and enhanced yield.
    Type: Grant
    Filed: February 13, 1986
    Date of Patent: August 4, 1987
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kohhei Kishi, Mitsuhiro Koden, Fumiaki Funada
  • Patent number: 4486748
    Abstract: A system for driving a segmented type liquid crystal display comprising a thin film transistor (TFT) array including a plurality of TFTs each having a gate line, a source line, and a drain line, a pair of substrates with one carrying the thin film transistor array coupled to a plurality of segmented display electrodes and the other carrying a common electrode opposite to the segmented display electrodes, a liquid crystal material interposed between the pair of substrates. The system is characterized by a source line and drain line driving circuit for driving the source line and the drain line with a first voltage waveform and a second voltage waveform in such a manner that the ratio of the first voltage amplitude to the second voltage is so selected that both charging and discharging voltages in the forward and backward directions are zero when the TFTs are off.
    Type: Grant
    Filed: September 16, 1982
    Date of Patent: December 4, 1984
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Keisaku Nonomura, Masataka Matsuura, Hisashi Uede, Kohhei Kishi, Hiroaki Kato
  • Patent number: 4469568
    Abstract: A method for making a thin-film transistor wherein a gate insulating layer is formed by anodizing two oxide layers on the substrate and then etching the assembly to completely remove the uppermost one of these layers to leave the lowermost layer so as to serve as the gate insulating layer.
    Type: Grant
    Filed: December 1, 1982
    Date of Patent: September 4, 1984
    Assignees: Sharp Kabushiki Kaisha, Japan Electronic Industry Development Association
    Inventors: Hiroaki Kato, Kohhei Kishi, Yutaka Takafuji
  • Patent number: 4451554
    Abstract: A method of forming a thin-film pattern such as a thin-film circuit component comprises successive formation of a first metal layer and then a photo resist layer on a substrate by the utilization of a photoetching technique. The substrate having the first metal layer and the photo resist layer on the top of the first metal layer is deposited with second metal layers which are discontinued from each other, one of the second metal layers being deposited on the top of the photo resist layer while the other of the second metal layers is deposited directly on the substrate around the first metal layer. The substrate assembly is then immersed into a solvent bath to remove the photo resist layer together with the second metal layer resting thereon and is thereafter immersed into an etchant bath to remove the first metal layer, leaving the second metal layer on the substrate.
    Type: Grant
    Filed: July 30, 1982
    Date of Patent: May 29, 1984
    Assignees: Sharp Kabushiki Kaisha, Japan Electronic Industry Development Association
    Inventors: Kohhei Kishi, Hiroaki Kato, Masataka Matsuura, Tomio Wada
  • Patent number: 4385292
    Abstract: A system is disclosed for driving a segmented type liquid crystal display comprising a thin film transistor (TFT) array including a plurality of TFTs each having a gate line, a source line, and a drain line, a pair of substrates with one carrying the thin film transistor array coupled to a plurality of segmented display electrodes and the other carrying a common electrode opposite to the segmented display electrodes, a liquid crystal material interposed between the pair of substrates. The system is characterized by a source line and drain line driving circuit for driving the source line and the drain line with a first voltage waveform and a second voltage waveform in such a manner that the ratio of the first voltage amplitude to the second voltage is so selected that both charging and discharging voltages in the forward and backward directions are zero when the TFTs are off.
    Type: Grant
    Filed: July 25, 1980
    Date of Patent: May 24, 1983
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Keisaku Nonomura, Masataka Matsuura, Hisashi Uede, Kohhei Kishi, Hiroaki Kato