Abstract: A data processing system which has a processor which issues a key sensing signal when waiting for the input of data; a discriminator connected to the processor for judging whether a key sensing signal is received from the processor and for generating a first signal; a controller for generating a second signal in response to the first signal received from the discriminator; and a switch for selecting one of a plurality of clock signals of different frequency to be sent to the processor in response to the second signal received from the controller. Generation of the second signal can be delayed by a first predetermined time, and a second predetermined time during which the key sensing signal is not received can be measured, whereby it is unnecessary to modify an application program to control the supply of power to the processor and only modification of a key sensing routine (BIOS) enables realization of positive power saving.

Abstract: A storage control apparatus for controlling memory elements having a data hold mode is provided with a switching circuit for switching a first voltage for a normal operation mode and a second voltage for the data hold mode as a power supply voltage applied to the memory elements, and a control circuit for controlling the switching operation of the switching circuit in accordance with accessing conditions of the memory elements. The control circuit is adapted to monitor accessing conditions of the respective memory elements and control the switching circuit to set all or a part of the memory elements except for accessed memory elements in the data hold mode.