Patents by Inventor Kohichi Nakayama

Kohichi Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9720113
    Abstract: A muon tracker includes a drift tube detector having a plurality of drift tube arrays, a detection time-difference calculation circuit configured to calculate a detected time-difference between a plurality of time data detected at least two of the drift tubes, a time-difference information database that stores a relationship between a plurality of predetermined tracks of the muon passing the drift tube detector and a predetermined time-difference of possible detected time data to be detected at least two of the drift tubes where each of the plurality of predetermined tracks passes, a time-difference referring circuit configured to refer the detected time-difference calculated at the detection time-difference calculation circuit with the predetermined time-difference stored in the time-difference information database, and a muon track determining circuit configured to determine a muon track as the predetermined track of the muon corresponding to the predetermined time-difference that matches the best with the
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kohichi Nakayama, Haruo Miyadera, Kenichi Yoshioka, Tsukasa Sugita, Naoto Kume, Yuichiro Ban
  • Publication number: 20160377747
    Abstract: A muon tracker includes a drift tube detector having a plurality of drift tube arrays, a detection time-difference calculation circuit configured to calculate a detected time-difference between a plurality of time data detected at least two of the drift tubes, a time-difference information database that stores a relationship between a plurality of predetermined tracks of the muon passing the drift tube detector and a predetermined time-difference of possible detected time data to be detected at least two of the drift tubes where each of the plurality of predetermined tracks passes, a time-difference referring circuit configured to refer the detected time-difference calculated at the detection time-difference calculation circuit with the predetermined time-difference stored in the time-difference information database, and a muon track determining circuit configured to determine a muon track as the predetermined track of the muon corresponding to the predetermined time-difference that matches the best with the
    Type: Application
    Filed: January 14, 2015
    Publication date: December 29, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kohichi NAKAYAMA, Haruo MIYADERA, Kenichi YOSHIOKA, Tsukasa SUGITA, Naoto KUME, Yuichiro BAN
  • Patent number: 9423361
    Abstract: An inner image generating apparatus includes a first receiver configured to receive an inlet track information and a first passage time of a muon, a second receiver configured to receive an outlet track information and a second passage time of the muon, a displacement calculator configured to calculate a track displacement of a track of the muon based on the inlet and outlet track information, a mean energy calculator configured to calculate a mean energy of the muon based on a time-difference between the first passage and the second passage time, a data integration circuit configured to integrate multiplied data multiplying the track displacement and the mean energy on a projected plane, and an image generating circuit configured to generate an inner image of the structure by identifying a position of matter at the projected plane based on an integrated multiplied data.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: August 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa Sugita, Haruo Miyadera, Kenichi Yoshioka, Naoto Kume, Kohichi Nakayama, Yuichiro Ban, Yoshiji Karino, Kyouichi Fujita, Shigeru Odanaka
  • Publication number: 20150198542
    Abstract: An inner image generating apparatus includes a first receiver configured to receive an inlet track information and a first passage time of a muon, a second receiver configured to receive an outlet track information and a second passage time of the muon, a displacement calculator configured to calculate a track displacement of a track of the muon based on the inlet and outlet track information, a mean energy calculator configured to calculate a mean energy of the muon based on a time-difference between the first passage and the second passage time, a data integration circuit configured to integrate multiplied data multiplying the track displacement and the mean energy on a projected plane, and an image generating circuit configured to generate an inner image of the structure by identifying a position of matter at the projected plane based on an integrated multiplied data.
    Type: Application
    Filed: January 14, 2015
    Publication date: July 16, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa SUGITA, Haruo MIYADERA, Kenichi YOSHIOKA, Naoto KUME, Kohichi NAKAYAMA, Yuichiro BAN, Yoshiji KARINO, Kyouichi FUJITA, Shigeru ODANAKA
  • Patent number: 9057682
    Abstract: According to the embodiment, there is provided a blade vibration measuring apparatus, having, a contactless displacement sensor which outputs a displacement measurement signal as measuring a displacement of a turbine moving blade in a rotation axis direction, a blade top position identifying device which outputs a blade top position identification signal to identify a top position based on a distance between the contactless displacement sensor and the top position of the turbine moving blade as receiving the displacement measurement signal output from the contactless displacement sensor, and a blade vibration calculating device which calculates vibration amplitude and a vibration frequency of the turbine moving blade based on temporal variation of the distance between the contactless displacement sensor and the top position of the turbine moving blade as receiving the blade top position identification signal output from the blade top position identifying device.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 16, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kohichi Nakayama, Kenji Osaki, Hisashi Matsuda, Hitoshi Sakakida, Toshio Hirano, Toshiaki Hirate, Sueyoshi Mizuno, Ikuo Saito
  • Publication number: 20130247671
    Abstract: According to the embodiment, there is provided a blade vibration measuring apparatus, having, a contactless displacement 5 sensor which outputs a displacement measurement signal as measuring a displacement of a turbine moving blade in a rotation axis direction, a blade top position identifying device which outputs a blade top position identification signal to identify a top position based on a distance between the contactless displacement sensor 10 and the top position of the turbine moving blade as receiving the displacement measurement signal output from the contactless displacement sensor, and a blade vibration calculating device which calculates vibration amplitude and a vibration frequency of the turbine moving blade based on temporal variation of the distance 15 between the contactless displacement sensor and the top position of the turbine moving blade as receiving the blade top position identification signal output from the blade top position identifying device.
    Type: Application
    Filed: September 13, 2012
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kohichi Nakayama, Kenji Osaki, Hisashi Matsuda, Hitoshi Sakakida, Toshio Hirano, Toshiaki Hirate, Sueyoshi Mizuno, Ikuo Saito
  • Patent number: 7802225
    Abstract: In the present invention, there is provided an optical proximity correction method including steps of: extracting a gate length distribution of a gate from a pattern shape of the gate of a transistor to be formed on a wafer; calculating electric characteristics of the gate; determining a gate length of a rectangular gate having electric characteristics equivalent to the calculated electric characteristics; calculating a corrective coefficient for describing an associated relationship between a statistical value of the extracted gate length distribution and the determined gate length; extracting a gate length distribution of a gate of a transistor by printing the design pattern, and calculating a gate length distribution representative value from the statistical value of the gate length distribution using the calculated corrective coefficient; and correcting the design pattern so that the calculated gate length distribution representative value will be a specification value.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: September 21, 2010
    Assignee: Sony Corporation
    Inventors: Kaoru Koike, Kohichi Nakayama
  • Patent number: 7541117
    Abstract: Disclosed herein is a mask pattern generating method for generating a mask pattern to be formed in a Levenson phase shift mask used in a light exposure process for exposing a photoresist film formed on a fabricated film to be patterned into a conductive layer to light when the conductive layer is patterned by photolithography, the conductive layer including a gate electrode formed in an active region extending in a first direction in a wafer in such a manner as to extend in a second direction orthogonal to the first direction, the mask pattern generating method including: a phase shifter arranging step; a shifter pattern image obtaining step; a trim pattern image obtaining step; and a phase shifter elongating step.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: June 2, 2009
    Assignee: Sony Corporation
    Inventors: Kazuhisa Ogawa, Satomi Nakamura, Kohichi Nakayama
  • Publication number: 20080263483
    Abstract: In the present invention, there is provided an optical proximity correction method including steps of: extracting a gate length distribution of a gate from a pattern shape of the gate of a transistor to be formed on a wafer; calculating electric characteristics of the gate; determining a gate length of a rectangular gate having electric characteristics equivalent to the calculated electric characteristics; calculating a corrective coefficient for describing an associated relationship between a statistical value of the extracted gate length distribution and the determined gate length; extracting a gate length distribution of a gate of a transistor by printing the design pattern, and calculating a gate length distribution representative value from the statistical value of the gate length distribution using the calculated corrective coefficient; and correcting the design pattern so that the calculated gate length distribution representative value will be a specification value.
    Type: Application
    Filed: February 6, 2008
    Publication date: October 23, 2008
    Applicant: SONY CORPORATION
    Inventors: Kaoru Koike, Kohichi Nakayama
  • Publication number: 20070283313
    Abstract: Disclosed herein is a mask pattern generating method for generating a mask pattern to be formed in a Levenson phase shift mask used in a light exposure process for exposing a photoresist film formed on a fabricated film to be patterned into a conductive layer to light when the conductive layer is patterned by photolithography, the conductive layer including a gate electrode formed in an active region extending in a first direction in a wafer in such a manner as to extend in a second direction orthogonal to the first direction, the mask pattern generating method including: a phase shifter arranging step; a shifter pattern image obtaining step; a trim pattern image obtaining step; and a phase shifter elongating step.
    Type: Application
    Filed: April 16, 2007
    Publication date: December 6, 2007
    Applicant: SONY CORPORATION
    Inventors: Kazuhisa Ogawa, Satomi Nakamura, Kohichi Nakayama
  • Publication number: 20060143172
    Abstract: Based on design data 151 and mask characteristic data 152 indicating at least the characteristics of a complementary stencil mask, generating alignment marks, designing membrane shapes, performing PUF division and boundary processing, complementarily dividing the mask, stitching, arranging complementary patterns, verifying pattern shapes, making corrections in the membrane, configuring the mask, verifying exposure, making corrections by inverting the mask, verifying the results of correction, converting the data, and thereby generating the drawing membrane data and drawing pattern data.
    Type: Application
    Filed: February 4, 2004
    Publication date: June 29, 2006
    Inventors: Isao Ashida, Kohichi Nakayama
  • Patent number: 7010434
    Abstract: A complementary division condition determining method and program and a complementary division method able to propose the optimum complementary division conditions for suppressing pattern displacement and mask destruction, wherein an internal stress of a mask is determined based on a displacement of a peripheral mark in a case when forming an opening in the mask and this value is used for first analysis (step ST12), pattern displacement and stress concentration occurring due to openings of split patterns are analyzed based on a first analysis model in a first analysis (step ST13), and a displacement due to external force of the membrane between the split patterns is analyzed in a second analysis (step ST14).
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: March 7, 2006
    Assignee: Sony Corporation
    Inventors: Isao Ashida, Kohichi Nakayama
  • Publication number: 20040210423
    Abstract: A complementary division condition determining method and program and a complementary division method able to propose the optimum complementary division conditions for suppressing pattern displacement and mask destruction, wherein an internal stress of a mask is determined based on a displacement of a peripheral mark in a case when forming an opening in the mask and this value is used for first analysis (step ST12), pattern displacement and stress concentration occurring due to openings of split patterns are analyzed based on a first analysis model in a first analysis (step ST13), and a displacement due to external force of the membrane between the split patterns is analyzed in a second analysis (step ST14). The order of the first and second analyses is not important.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 21, 2004
    Inventors: Isao Ashida, Kohichi Nakayama