Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and configured to generate a performance model for calculating a performance value of an application program from a power restriction for each set of parameters of the application program, based on data acquired when a computing apparatus executes the application program for each set of parameters of the application program under each of a plurality of power restrictions; calculate, for each set of parameters of the application program, the performance value of the application program from a first power restriction different from any of the plurality of power restrictions, based on the performance model generated for each set of parameters of the application program; and output a set of parameters of the application program corresponding to a highest performance value of the calculated performance values.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor performs first all-reduce communication with another information processing apparatus coupled to a first leaf switch coupled to the information processing apparatus, performs second all-reduce communication with one information processing apparatus coupled to a second leaf switch included in the same layer as the first leaf switch and third all-reduce communication with one information processing apparatus coupled to a third leaf switch which is coupled to a spine switch coupled to the first leaf switch included in a layer different from the layer including the first leaf switch, using a result of the first all-reduce communication, and transmits a result of a process of the second all-reduce communication and the third all-reduce communication to the another information processing apparatus coupled to the first leaf switch.

Abstract: An apparatus causes a management unit included in an arithmetic processing unit to manage, where an executable task is included in a queue, execution of the task. The apparatus causes a standby unit included in the arithmetic processing unit to execute, when the executable task is not included in the queue, a decision process for deciding, by polling, whether information from another apparatus different from the apparatus is received by a communication controller until the executable task is included in the queue.

Abstract: A communication system includes a plurality of leaf switches connected to a plurality of spine switches in topology of a Latin square Fat-Tree, and a plurality of information processing apparatus, wherein each of the information processing apparatuses performs first all reducing, wherein each of first information processing apparatuses performs second all reducing, on the basis of the result of the first all reducing, between the first information processing apparatus and another first information processing apparatus connected to a leaf switch connected to a first spine switch corresponding to a first direction in an area, wherein each of the first information processing apparatuses performs third all reducing, on the basis of the result of the second all reducing, between the first information processing apparatus and another first information processing apparatus connected to a leaf switch connected to a second spine switch corresponding to a second direction in the area.

Abstract: An apparatus is configured to calculate consumption power of a processor caused by execution of a program, based on sampling data acquired by event-based sampling. The apparatus determines whether the processor is in an idle state, by using the sampling data of a clock event, where the clock event is an event which generates an interrupt at fixed time intervals when the processor is not in the idle state, and which generates the interrupt when a state of the processor changes from the idle state to a non-idle state. In a case where the processor is in the idle state, the apparatus calculates a first amount of consumption power of the processor in the idle state, based on a second amount of consumption power calculated using a consumption power model and a third amount of consumption power included in the sampling data.

Abstract: An information processing device includes a memory storing information indicating a virtual address space for data to be processed; and a processor that executes, via the virtual address space, a given process on the data to be processed, monitors access from the processor to multiple monitoring regions among a plurality of regions included in the virtual address space and have been set as targets to be monitored, and executes given control based on an accessed monitoring region among the multiple monitoring regions and for which the access has been detected by the processor.

Abstract: An information processing system includes a plurality of switches connected to each other in a form of a full mesh and a plurality of information processing apparatuses respectively connected to any one of the plurality of switches. A first information processing apparatus of the plurality of information processing apparatuses includes a processor. The processor is configured to generate a second identifier by calculating an exclusive OR of a first identifier and a first number corresponding to a communication phase. The first identifier identifies a first switch connected to the first information processing apparatus. The first number is included in a set of linearly independent numbers allocated to the first information processing apparatus. The processor is configured to perform communication with a second information processing apparatus of the plurality of information processing apparatuses. The second information processing apparatus is connected to a second switch having the second identifier.

Abstract: An information processing system includes leaf switches connected in a form of a Latin square fat tree, information processing apparatuses connected to any one of the leaf switches, respectively, and a management apparatus including a first processor. The first processor extracts one or more rows and one or more columns from a lattice portion other than an infinite original point of a finite projection plane corresponding to the Latin square fat tree. The first processor specifies leaf switches corresponding to points included in the extracted one or more rows and included in the extracted one or more columns. The first processor transmits an instruction to execute an all-reduce communication, in which a result of the communication is shared by all members that execute the communication, to a predetermined number of information processing apparatuses among the information processing apparatuses connected to the specified leaf switches.

Abstract: An information processing apparatus including a communication interface to communicate with another information processing apparatus, and a processor that executes a process including issuing, by a first thread, a reception request of data from the another information processing apparatus to the communication interface, determining, by using the first thread, whether a completion notification is stored in a queue that stores data transmitted from the other information processing apparatus, causing the first thread to transit to a suspended state when the completion notification is not stored, executing a processing by using a second thread included in the plurality of threads when the first thread is in the suspended state, determining whether the completion notification is stored in the queue after the processing, and transferring the received data to the first thread and causing the first thread to return from the suspended state, upon a storing of the completion notification.

Abstract: An information processing system includes Spine switches, Leaf switches coupled to the Spine switches in a form of a Latin square fat tree, and apparatuses each coupled to any one of the Leaf switches and including a processor. The processor performs, in a case where the processor is included in one of first apparatuses coupled to one of first Leaf switches, first collective communication with others of the first apparatuses on a route via a first Spine switch. The first Leaf switches correspond to at least a portion of points other than points at infinity of a finite projective plane corresponding to the Latin square fat tree. The processor performs second collective communication with others of the first apparatuses on a route via a second Spine switch at each phase of the first collective communication. The second Spine switch is different from the first Spine switch.

Abstract: An apparatus stores connection information indicating connection relationship among topological structures in a network, in which first-type topological structures are coupled to second-type topological structures. The apparatus stores first transfer-patterns each indicating a combination of input and output ports for performing all-to-all communication without path conflict in each of the first-type topological structures, and second transfer-patterns each indicating a combination of input and output ports for performing all-to-all communication without path conflict in each of the second-type topological structures.

Abstract: An information processing device includes a memory, and a plurality of processor cores that access the memory. The plurality of processor cores respectively executes processes to be executed by the plurality of processor cores in accordance with execution priority levels of the processes. When a polling process for repeatedly determining whether reception data for input/output processing is received is underway in one of the plurality of processor cores, the plurality of processor cores respectively executes the input/output processing in response to a determination, made by the polling process, that the reception data have been received, and when the polling process is not underway in any of the plurality of processing cores, the plurality of processor cores respectively executes the input/output processing in response to a processor interrupt issued upon reception of the reception data.

Abstract: A system includes spine switches, leaf switches, information processing apparatuses, and a processor configured to allocate a first leaf switch group to a first job, the first leaf switch group corresponding to a first column in a lattice part including points other than points at infinity of a finite projective plane corresponding to a Latin square fat-tree, and allocate a second leaf switch group to a second job, the second leaf switch group corresponding a second column, and transmit first schedule information on first communication related to the first job to a first information processing apparatus coupled to the first leaf switch group, and transmit second schedule information on second communication related to the second job to a second information processing apparatus coupled to the second leaf switch group, wherein the first and second communication are collective communication in which each of the information processing apparatuses communicates with others.

Abstract: In extendedly allocating a job to nodes subordinate to multiple leaf switch, the job is allocated to nodes of each of multiple leaf switches such that that the number of the nodes being allocated thereto the job and belonging to each of the multiple leas switches does not exceed the number of valid links between the leaf switch and the spine switches. This can avoid occurrence of a conflict accompanied by a link failure, so that degrading of the system can be avoided.

Abstract: An information processing system includes switches coupled to each other in a form of a Latin square fat-tree and apparatuses coupled to the switches. A processor of a first apparatus coupled to one of first switches executes a first reduce with others of the first apparatuses. A processor of a second apparatus coupled to a representative switch executes a second reduce with representative apparatuses of respective switches belonging to a group corresponding to the second apparatus. The processor of the second apparatus executes Allreduce with others of the second apparatuses and transmits the result of the Allreduce to the representative apparatuses of the respective switches belonging to the group corresponding to the second apparatus. A processor of a representative apparatus that receives the result of the Allreduce transmits the result of the Allreduce to others of apparatuses coupled to a switch to which the representative apparatus is coupled.

Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and the processor configured to exclude a combination for satisfying a condition from multiple combinations each including a number of shifts of multiple switch layers in a fat-tree network using Latin square, create relay settings for multiple switches for performing communication through multiple communication paths corresponding to remain combinations except the combination excluded from the multiple combinations, and transmit correspondingly the created relay settings to the multiple switches.

Abstract: A system includes circuitry configured to execute a first thread of a plurality of threads, measure an execution time period during which the circuitry executes the first thread without executing other threads of the plurality of threads, determine whether the measured execution time period exceeds a threshold value, specify first address information of a first instruction which is included in the first thread when it is determined that the measured execution time period exceeds the threshold value, the first instruction being an instruction that is scheduled to be executed, exchange the first instruction stored in an address region specified by the first address information with a second instruction instructing the circuitry to switch from executing the first thread to executing a second thread of the plurality of threads, and switch from executing the first thread to the executing the second thread by executing the second instruction.

Abstract: First information includes a sequence of first picking-numbers and a sequence of first sets including input-port identification values for a second number of first topological structures. Second information includes a sequence of second picking-numbers and a sequence of second sets including output-port identification values for a first number of second topological structures. Based on the first and second information, an apparatus determines first and second target picking-numbers so that a product of the first and second target picking-numbers is equal to or greater than a given number smaller than a product of the first and second numbers.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor performs first all-reduce communication with another information processing apparatus coupled to a first leaf switch coupled to the information processing apparatus, performs second all-reduce communication with one information processing apparatus coupled to a second leaf switch included in the same layer as the first leaf switch and third all-reduce communication with one information processing apparatus coupled to a third leaf switch which is coupled to a spine switch coupled to the first leaf switch included in a layer different from the layer including the first leaf switch, using a result of the first all-reduce communication, and transmits a result of a process of the second all-reduce communication and the third all-reduce communication to the another information processing apparatus coupled to the first leaf switch.

Abstract: A parallel computer system includes a plurality of network switches that are all connected to each other, and a plurality of nodes each connected to one of the plurality of network switches, where each network switch is connected to two or more nodes of the plurality of nodes. Each node determines a first destination node of data to be transmitted by the each node at a given time so that a first network switch connected to the first destination node is different from a second network switch connected to a second destination node of data transmitted by any node, other than the each node, which is connected to a network switch to which the each node is connected, and transmits data to the determined first destination node.